| c45fbe1bd590 ("drm/amd/sriov skip jped ip block and close pgcg flags") |
| 1b0443b11530 ("drm/amdgpu: fix coding error of mmhub pg enablement") |
| b794616d1f6c ("drm/amd/powerplay: enable athub pg") |
| 6fb176a75574 ("drm/amd/powerplay: enable MM DPM PG for sienna_cichlid (v2)") |
| 4d72dd12f086 ("drm/amdgpu: enable JPEG3.0 for Sienna_Cichlid") |
| b467c4f5b4af ("drm/amdgpu: enable JPEG3.0 PG and CG for Sienna_Cichlid") |
| b8f10585cb20 ("drm/amdgpu: enable VCN3.0 for Sienna_Cichlid") |
| e823be13dbc2 ("drm/amdgpu: enable VCN3.0 PG and CG for Sienna_Cichlid") |
| a346ef86a97f ("drm/amdgpu: add mes block to sienna_cichlid") |
| 02bb391d916a ("drm/amd/powerplay: make gfx ds can be configure for sienna_cichlid") |
| 094cdf15e995 ("drm/amdgpu/powerplay: set Thermal control for sienna_cichlid") |
| 983ab9f2842e ("drm/amd/powerplay: enable SOC Clock Deep Sleep for sienna_cichlid") |
| 15dbe18fa634 ("drm/amd/powerplay: enable Graphics Clock Deep Sleep for sienna_cichlid") |
| 62c1ea6bbab7 ("drm/amd/powerplay: enable Ultra Low Voltage for sienna_cichlid") |
| 4cd4f45b6507 ("drm/amd/powerplay: set FCLK DPM for sienna_cichlid") |
| fea905d47125 ("drm/amd/powerplay: set SOCCLK DPM for sienna_cichlid") |
| b455159c0531 ("drm/amdgpu/powerplay: add initial swSMU support for sienna_cichlid (v2)") |
| 157e72e831cb ("drm/amdgpu: add sdma ip block for sienna_cichlid (v5)") |
| 933c8a93e241 ("drm/amdgpu: add gfx ip block for sienna_cichlid (v3)") |
| 757b3af8ecb4 ("drm/amdgpu: add ih ip block for sienna_cichlid") |
| 0b3df16b5abc ("drm/amdgpu: add gmc ip block for sienna_cichlid") |
| 2e1ba10e9271 ("drm/amdgpu/soc15: add common ip block for sienna_cichlid") |
| 117910ed92b3 ("drm/amdgpu/soc15: add support for sienna_cichlid") |
| 41fb666d5ceb ("drm/amd/powerplay: remove SRIOV check in SMU11 (v2)") |
| a16be2fe1455 ("drm/amd/powerplay: skip smu_i2c_eeprom_init/fini under sriov mode") |
| fa3d49f1e904 ("drm/amd/powerplay: remove the support of vega20 from swsmu") |
| 43a10b15d442 ("amd/amdgpu: Limit rlcg write registers only for nv12") |
| 38748ad88a2f ("drm/amdgpu: enable one vf mode for nv12") |
| b217e6f579d6 ("drm/amdgpu: clear the messed up checking logic") |
| f9b93c9ba605 ("drm/amd/powerplay: limit smu support to Arcturus for onevf") |
| e57761c68bb4 ("drm/amdgpu: cache smu fw version info") |
| 47c11cff7e44 ("drm/amd/powerplay: update Arcturus smu-driver if header") |
| 774e335b878c ("drm/amd/powerplay: properly set the dpm_enabled state") |
| 94e0805ba929 ("drm/amd/powerplay: correct i2c eeprom init/fini sequence") |
| 56ddddaaccbf ("drm/amd/powerplay: bump the NAVI10 smu-driver if version") |
| 1675c3a24d07 ("drm/amdgpu: stop disable the scheduler during HW fini") |
| 49e78c820a02 ("drm/amd/powerplay: move the ASIC specific nbio operation out of smu_v11_0.c") |
| 9644bf5f4ab8 ("drm/amdgpu/swSMU: handle manual AC/DC notifications") |
| 75610fdd38d9 ("drm/amdgpu/swSMU: set AC/DC mode based on the current system state (v2)") |
| 66c2f5db1fbd ("drm/amdgpu/swSMU: correct the bootup power source for Navi1X (v2)") |
| 2c02b38a10fc ("drm/amd/swSMU: add callback to set AC/DC power source (v2)") |
| 2e0cc4d48b91 ("drm/amdgpu: revise RLCG access path") |
| f88ef3ca869d ("drm/amdgpu/swsmu: clean up unused header in swsmu") |
| c1b6921209e3 ("drm/amd/powerplay: add smu if version for navi12") |
| 1da7d4a8ab79 ("drm/amdgpu: Write blocked CP registers using RLC on VF") |
| ae458c7b9dcc ("drm/amdgpu/powerplay: Remove deprecated smc_read_arg") |
| 1c58267cbe46 ("drm/amdgpu/powerplay: Refactor SMU message handling for safety") |
| 460c484f2411 ("drm/amdgpu: Initialize SPM_VMID with 0xf (v2)") |
| 7af8bc5016d9 ("drm/amd/powerplay: add DFCstate control pptable func for arct") |
| 5d8b936df284 ("drm/amdgpu/smu: properly handle runpm/suspend/reset") |
