| fcc6aa8f3e96 ("drm/i915/ehl: Implement W/A 22010492432") |
| 0e2497e334de ("drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock") |
| fc6200948275 ("drm/i915/icl+: Simplify combo/TBT PLL calculation call-chain") |
| 09eac8277262 ("drm/i915/tgl+: Fix TBT DPLL fractional divider for 38.4MHz ref clock") |
| 61b088c5374a ("drm/i915/ehl: Restrict w/a 1607087056 for EHL/JSL") |
| ccc495fd7ac3 ("drm/i915: Unify the DPLL ref clock frequency tracking") |
| b953eb2153a3 ("drm/i915/skl, cnl: Split out the WRPLL/LCPLL frequency calculation") |
| 350ab42f9735 ("drm/i915/hsw: Split out the WRPLL, LCPLL, SPLL frequency calculation") |
| 068f723ed554 ("drm/i915/hsw: Split out the SPLL parameter calculation") |
| 206b7edc356c ("drm/i915/hsw: Rename the get HDMI/DP DPLL funcs to get WRPLL/LCPLL") |
| c039b63a3d28 ("drm/i915/skl: Parametrize the DPLL ref clock instead of open-coding it") |
| 45e4728b87ad ("drm/i915: Move DPLL frequency calculation to intel_dpll_mgr.c") |
| 6cbcd57680e1 ("drm/i915/hsw: Use the DPLL ID when calculating DPLL clock") |
| 4ac7df1775f3 ("drm/i915: Move the DPLL vfunc inits after the func defines") |
| 353ad959a0bc ("drm/i915: Keep the global DPLL state in a DPLL specific struct") |
| 830b2cdcf4cc ("drm/i915: Move DPLL HW readout/sanitize fns to intel_dpll_mgr.c") |
| b48f4b3be920 ("drm/i915: Fix bounds check in intel_get_shared_dpll_id()") |
| 00535527350c ("drm/i915/crc: move pipe_crc from drm_i915_private to intel_crtc") |
| e57291c2d395 ("drm/i915/display/display: Make WARN* drm specific where drm_device ptr is available") |
| 1de143cc5b60 ("drm/i915/display/ddi: Make WARN* drm specific where drm_device ptr is available") |
| 93a0ed6cc164 ("drm/i915: split intel_modeset_driver_remove() to pre/post irq uninstall") |
| 926b005cd8c4 ("drm/i915: split out display debugfs to a separate file") |
| 06d3ff6e7451 ("drm/i915: move intel_csr.[ch] under display/") |
| 157ff3ab3227 ("drm/i915/dpll_mgr: convert to drm_device based logging macros.") |
| 6311d260a179 ("drm/i915/debugfs: Remove i915_energy_uJ") |
| 6db07ce48887 ("drm/i915/debugfs: conversion to drm_device based logging macros.") |
| 00376ccfb2a4 ("drm/i915: conversion to drm_device logging macros when drm_i915_private is present.") |
| 99bc73ec8deb ("drm/i915/display/dpll_mgr: Make WARN* drm specific where drm_device ptr is available") |
| eeec73f8a4a4 ("drm/i915/gt: Skip rmw for masked registers") |
| 0c2d55128f33 ("drm/i915: Store active_pipes bitmask in cdclk state") |
| 28a30b45f5e9 ("drm/i915: Convert cdclk to global state") |
| 0ef1905ecf2e ("drm/i915: Introduce better global state handling") |
| 5f34299384cb ("drm/i915: Move intel_atomic_state_free() into intel_atomic.c") |
| 4c029c499fb4 ("drm/i915: swap() the entire cdclk state") |
| 1965de63a93a ("drm/i915: Extract intel_cdclk_state") |
| 5604e9ceaed5 ("drm/i915: Simplify intel_set_cdclk_{pre,post}_plane_update() calling convention") |
| 0bb94e03834e ("drm/i915: s/cdclk_state/cdclk_config/") |
| 65c88a866d70 ("drm/i915: s/need_cd2x_updare/can_cd2x_update/") |
| b4db3a8c689b ("drm/i915: Collect more cdclk state under the same roof") |
| 54f09d2342b0 ("drm/i915: Move more cdclk state handling into the cdclk code") |
| 6dcde04706d8 ("drm/i915: Move linetime wms into the crtc state") |
| 0560b0c6b36c ("drm/i915: Polish WM_LINETIME register stuff") |
| 219cee8fe7ae ("drm/i915/debugfs: remove VBT data about DRRS") |
| cd1c4d4a22bc ("drm/i915/debugfs: remove i915_dpcd file") |
| dc008bf0aa09 ("drm/i915/display: use intel_de_*() functions for register access") |
| f7960e7f8f24 ("drm/i915/ddi: use intel_de_*() functions for register access") |
| 1c63f6dfc01d ("drm/i915/icl_dsi: use intel_de_*() functions for register access") |
| b3a723867117 ("drm/i915/dpll_mgr: use intel_de_*() functions for register access") |
| 3e9f55df59f7 ("drm/i915/cdclk: use intel_de_*() functions for register access") |
| d1b2828af0cc ("drm/i915: Fix modeset locks in sanitize_watermarks()") |
