| feb6329c58a8 ("drm/amdgpu: add gfx ip block for dimgrey_cavefish") |
| 771cc67ed08f ("drm/amdgpu: add ih ip block for dimgrey_cavefish") |
| 3e02ad447677 ("drm/amdgpu: add gmc ip block for dimgrey_cavefish") |
| 2aa92b12dfce ("drm/amdgpu: add common ip block for dimgrey_cavefish") |
| 88edbad6ed06 ("drm/amdgpu: set ip blocks for van gogh") |
| 6c266fb56cb8 ("drm/amdgpu: add gfx support for van gogh (v3)") |
| 6405e627a0ad ("drm/amdgpu: add gmc v10 supports for van gogh (v4)") |
| bd4f28117ef2 ("drm/amdgpu: add van gogh support for ih block") |
| 8ffff9b4499c ("drm/amdgpu: use function pointer for gfxhub functions") |
| 9fb1506eb671 ("drm/amdgpu: Use function pointer for some mmhub functions") |
| 01eee24fceb9 ("drm/amdgpu: enable umc 8.7 functions in gmc v10") |
| 2577db91e82e ("drm/amdgpu: add vmhub funcs helper (v2)") |
| 5befb6fc3b77 ("drm/amdgpu: add member to store vm fault interrupt masks") |
| c5b6c914d2f3 ("drm/amdgpu: enable cp_fw_write_wait for navy_flounder") |
| 8f8463dddcad ("drm/amdgpu: force pa_sc_tile_steering_override to 0 for navy_flounder") |
| c4a8b802869c ("drm/amdgpu: configure navy_flounder gfx according to gfx 10.3") |
| 885eb3fad6ff ("drm/amdgpu: add gfx ip block for navy_flounder") |
| 026c396b41a4 ("drm/amdgpu: add ih ip block for navy_flounder") |
| fc8f07da1f47 ("drm/amdgpu: add gmc ip block for navy_flounder") |
| 8515e0a489e0 ("drm/amdgpu: add common ip block for navy_flounder") |
| d463d8c964dd ("drm/amdgpu/gfx10: add clockgating support for navy_flounder") |
| 0287ac57b55d ("drm/amdgpu/gmc10: add navy_flounder support") |
| 650101930405 ("drm/amdgpu/gfx10: add support for navy_flounder firmware") |
| 1f9d56c30939 ("drm/amdgpu: add register distance members into vmhub structure") |
| fdb8483bd68e ("drm/amdgpu: add XGMI support for sienna cichlid") |
| 8db1015b99b2 ("drm/amdgpu/sriov : Use kiq to do tlb invalidation for gfx10 on sriov") |
| 3a2f0c813b42 ("drm/amdkfd: Support Sienna_Cichlid KFD v4") |
| 689dede0a0ee ("drm/amdgpu: enable 3D pipe 1 on Sienna_Cichlid") |
| 305401e77bf8 ("drm/amdgpu: force pa_sc_tile_steering_override to 0 for gfx10.3") |
| 263acd471f50 ("drm/amdgpu/gfx10: add gc golden setting for sienna_cichlid") |
| 58139a42dc08 ("drm/amdgpu/gfx10: change register configure for sienna_cichlid") |
| 933c8a93e241 ("drm/amdgpu: add gfx ip block for sienna_cichlid (v3)") |
| 757b3af8ecb4 ("drm/amdgpu: add ih ip block for sienna_cichlid") |
| 0b3df16b5abc ("drm/amdgpu: add gmc ip block for sienna_cichlid") |
| af01d47d3c22 ("drm/amdgpu: add support gfxhub for sienna_cichlid (v3)") |
| ffffb96d1165 ("drm/amdgpu: add support on mmhub for sienna_cichlid") |
| 2e1ba10e9271 ("drm/amdgpu/soc15: add common ip block for sienna_cichlid") |
| 2f7f522722ef ("drm/amdgpu/gfx10: add clockgating support for sienna_cichlid") |
| 57d706026fab ("drm/amdgpu/gmc10: add sienna_cichlid support") |
| 6c06333073ac ("drm/amdgpu/gfx10: add support for sienna_cichlid firmware") |
| 43a10b15d442 ("amd/amdgpu: Limit rlcg write registers only for nv12") |
| 4189425d309a ("drm/amdgpu: add SPM golden settings for Navi10(v2)") |
| d2155a719d8f ("drm/amdgpu: Print UTCL2 client ID on a gpuvm fault") |
| 1675c3a24d07 ("drm/amdgpu: stop disable the scheduler during HW fini") |
| 2e0cc4d48b91 ("drm/amdgpu: revise RLCG access path") |
| fe5211f19a74 ("drm/amdgpu: add reset_ras_error_count function for MMHUB") |
| f091c1c70e89 ("drm/amdgpu: disable 3D pipe 1 on Navi1x") |
| 1da7d4a8ab79 ("drm/amdgpu: Write blocked CP registers using RLC on VF") |
| 460c484f2411 ("drm/amdgpu: Initialize SPM_VMID with 0xf (v2)") |
| fd7d08bad7a4 ("drm/amdkfd: Make get_tile_config() generic") |
