| 1f61a43fcec1 ("drm/amd/sriov porting sriov cap to vcn3.0") | |
| 8606cf794f78 ("drm/amdgpu/vcn3.0: schedule instance 0 for decode and 1 for encode") | |
| cfcc06cd15bf ("drm/amdgpu: add pause DPG mode for VCN3.0") | |
| 65b17cc89898 ("drm/amdgpu: add stop DPG mode for VCN3.0") | |
| cf14826cdfb5 ("drm/amdgpu: add VCN3.0 support for Sienna_Cichlid") |