| 73263cb6e2fe ("drm/i915: Expose alpha formats on VLV/CHV primary planes") |
| 03b0ce9532ec ("drm/i915: Add support for half float framebuffers for gen4+ primary planes") |
| bb6ae9e653dc ("drm/i915: Allow planes to declare their minimum acceptable cdclk") |
| 1d5a95b5c943 ("drm/i915: Rework global state locking") |
| 993254292b9e ("drm/i915: Refactor timestamping constants update") |
| 3e30d70805d5 ("drm/i915: Make .modeset_calc_cdclk() mandatory") |
| 131d3b1af105 ("drm/i915: Stop using drm_atomic_helper_check_planes()") |
| 2e7f76c1e4b6 ("drm/i915: s/pipe_config/crtc_state/ in intel_crtc_atomic_check()") |
| fe4709a8d033 ("drm/i915: Extract intel_modeset_calc_cdclk()") |
| 933122cc7cd2 ("drm/i915: Remove duplicated bxt/cnl/icl .modeset_calc_cdclk() funcs") |
| 502d1c04f53c ("drm/i915: Reuse cnl_modeset_calc_cdclk() on icl+") |
| d2f429ebb977 ("drm/i915: Add calc_voltage_level display vfunc") |
| 751a93a15cde ("drm/i915: Consolidate {bxt,cnl,icl}_uninit_cdclk") |
| 1cbcd3b4b168 ("drm/i915: Combine bxt_set_cdclk and cnl_set_cdclk") |
| 736da8112fee ("drm/i915: Use literal representation of cdclk tables") |
| 71dc367e2bc3 ("drm/i915: Consolidate bxt/cnl/icl cdclk readout") |
| 71cd86cfaa12 ("drm/i915/tgl: Use refclk/2 as bypass frequency") |
| 3d1da92baffe ("drm/i915: Add 324mhz and 326.4mhz cdclks for gen11+") |
| 385ba629aa1c ("drm/i915: Allow /2 CD2X divider on gen11+") |
| d06a79d33e0f ("drm/i915: Use enum pipe instead of crtc index to track active pipes") |
| 5b51f28fa7ba ("drm/i915/sprite: un-inline icl_is_hdr_plane()") |
| 801404632c4b ("drm/i915/display: Drop kerneldoc for 'intel_atomic_commit'") |
| a85fb46777c0 ("drm/i915: Use intel_ types in intel_atomic_commit()") |
| 6a64e985d242 ("drm/i915: Use intel_ types in intel_{lock,modeset}_all_pipes()") |
| 5c28e3a567fe ("drm/i915: Clear the shared PLL from the put_dplls() hook") |
| 94e35ce22173 ("drm/i915: Cosmetic fix for skl+ plane switch statement") |
| 26443a4bc448 ("drm/i915: Add windowing for primary planes on gen2/3 and chv") |
| 24a7bfe0c2d7 ("drm/i915: Keep the TypeC port mode fixed when the port is active") |
| eea72c4c2161 ("drm/i915/icl: Reserve all required PLLs for TypeC ports") |
| 726ca99666db ("drm/i915/icl: Split getting the DPLLs to port type specific functions") |
| 01b24f50b67f ("drm/i915: Sanitize the shared DPLL find/reference interface") |
| 866955fa452e ("drm/i915: Sanitize the shared DPLL reserve/release interface") |
| 8c10e2262663 ("drm/i915: Keep the TypeC port mode fixed for detect/AUX transfers") |
| 32691b58d157 ("drm/i915: Fix the TypeC port mode sanitization during loading/resume") |
| 1cd5ef6ee23c ("drm/i915: Sanitize the TypeC connect/detect sequences") |
| 424f109f5c5d ("drm/i915: Handle the TCCOLD power-down event") |
| ddec362724f9 ("drm/i915: Wait for TypeC PHY complete flag to clear in safe mode") |
| c905eb28bd3f ("drm/i915: Factor out common parts from TypeC port handling functions") |
| ab7bc4e1a550 ("drm/i915: Unify the TypeC port notation in debug/error messages") |
| dd7239c545b1 ("drm/i915: Use the correct AUX power domain in TypeC TBT-alt mode") |
| e9b7e1422d40 ("drm/i915: Sanitize the terminology used for TypeC port modes") |
| bc85328ff431 ("drm/i915: Move the TypeC port handling code to a separate file") |
| 39a5883f8670 ("drm/i915/icl: Add support to read out the TBT PLL HW state") |
| 4f25720b2c04 ("drm/i915: Pass intel state to plane functions as well") |
| 3b4bf24d27e0 ("drm/i915: Convert hw state verifier to take more intel state, v2.") |
| 855e0d684a3e ("drm/i915: Convert most of atomic commit to take more intel state") |
| 69f786aea946 ("drm/i915: Pass intel_crtc_state to needs_modeset()") |
| 63c9dae71dc5 ("drm/i915/ehl: Add voltage level requirement table") |
| 9c811fce8a44 ("drm/i915/icl: Add new supported CD clocks") |
| b124ea432af7 ("drm/i915: Constify intel_pipe_config_compare()") |
