| 07685c827b2a ("drm/i915/icl: Implement voltage swing programming sequence for MG PHY DDI") |
| fb5c8e9d4350 ("drm/i915/icl: Implement voltage swing programming sequence for Combo PHY DDI") |
| f3cf4ba45e13 ("drm/i915: Pass encoder type to cnl_ddi_vswing_sequence() explicitly") |
| cf3e0fb48cdb ("drm/i915/cnl: Move ddi buf trans related functions up.") |
| cc9cabfdec38 ("drm/i915/cnl: Move voltage check into ddi buf trans functions.") |
| 381f957044d0 ("drm/i915: Enable voltage swing before enabling DDI_BUF_CTL.") |
| 2f7460a75aa4 ("drm/i915: Align vswing sequences with old ddi buffer registers.") |
| d509af6c85bb ("drm/i915: decouple gen9 and gen10 dp signal levels.") |
| 1b6e2fd2896a ("drm/i915: Introduce intel_ddi_dp_level.") |
| 50946c89850d ("drm/i915: Return correct EDP voltage swing table for 0.85V") |
| 61f3e7704897 ("drm/i915/cnl: Add missing type case.") |
| 0091abc3a621 ("drm/i915/cnl: Enable loadgen_select bit for vswing sequence") |
| cf54ca8bc567 ("drm/i915/cnl: Implement voltage swing sequence.") |
| d8d4a512a6ff ("drm/i915/cnl: Implement CNL display init/unit sequence") |
| ef4f7a689ac5 ("drm/i915/cnl: Implement .set_cdclk() for CNL") |
| 945f2672ccbb ("drm/i915/cnl: Implement .get_display_clock_speed() for CNL") |
| e1cd3325b7a7 ("drm/i915: move the {skl, bxt}_{i, uni}nit_cdclk declarations") |
| 3dc38eea665f ("drm/i915: Remove direct usages of intel_crtc->config from DDI code") |
| e9ce1a625fca ("drm/i915: Pass intel_crtc to DDI functions called from crtc en/disable") |
| 62b695662a24 ("drm/i915: Only enable DDI IO power domains after enabling DPLL") |
| 71cc22e5db89 ("drm/i915/glk: Don't enable DDI IO power domains during init") |
| f4f4b59be52b ("drm/i915/glk: Implement WaDDIIOTimeout") |
| ffe5111e28e5 ("drm/i915: Introduce intel_ddi_dp_voltage_max()") |
| 7d1c42e679f9 ("drm/i915: Refactor code to select the DDI buf translation table") |
| 24dbf51a5517 ("drm/i915: struct_mutex is not required for allocating the framebuffer") |
| 70001cd25654 ("drm/i915: Remove struct_mutex for destroying framebuffers") |
| 370a81fb89cb ("drm/i915: Remove unused function intel_ddi_get_link_dpll()") |
| d8fc70b7367b ("drm/i915: Make power domain masks 64 bit long") |
| 49cd97a35d90 ("drm/i915: Start moving the cdclk stuff into a distinct state structure") |
| 8f0cfa4d2a62 ("drm/i915: Pass computed vco to bxt_set_cdclk()") |
| 7ff89ca21358 ("drm/i915: Move most cdclk/rawclk related code to intel_cdclk.c") |
| 4717e8bb7341 ("drm/i915: Clean up the .get_cdclk() assignment if ladder") |
| c49a0d054a05 ("drm/i915: s/get_display_clock_speed/get_cdclk/") |
| 4e841ecd4e18 ("drm/i915: Nuke intel_mode_max_pixclk()") |
| a7d1b3f41a2d ("drm/i915: Store the pipe pixel rate in the crtc state") |
| 3c779a49bd7c ("drm/i915: Avoid BIT(max) - 1 and use GENMASK(max - 1, 0)") |
| 6248017ae530 ("drm/i915: Get correct display clock on 945gm") |
| 9fb5026f857d ("drm/i915/glk: Turn on workarounds that apply to Geminilake too") |
| b976dc53ec43 ("drm/i915: Introduce IS_GEN9_BC for Skylake and Kabylake.") |
| 8da53efaa228 ("drm/i915/kbl: Apply WaIncreaseDefaultTLBEntries on KBL.") |
| 32ebc292119a ("drm/i915: Remove BXT restore arbitration around ctx switch") |
| 31bb2ef97ea9 ("drm/i915: Check for NULL atomic state in intel_crtc_disable_noatomic()") |
| a8cd6da0c0d5 ("drm/i915: Remove crtc->config usage from intel_modeset_readout_hw_state()") |
| 1d4258db3e0b ("drm/i915: Remove useless casts to intel_plane_state") |
| 957870f93412 ("drm/i915: Split out i915_gem_object_set_tiling()") |
| 254e0931f5b9 ("drm/i915/glk: Convert a few more IS_BROXTON() to IS_GEN9_LP()") |
| 91d4e0aa923e ("drm/i915: Move ggtt fence/alignment to i915_gem_tiling.c") |
| 944397f04f24 ("drm/i915: Store required fence size/alignment for GGTT vma") |
| 0d4e8f1dbcab ("drm/i915: Replace WARNs in fence register writes with extensive asserts") |
| 5b30694b474d ("drm/i915: Align GGTT sizes to a fence tile row") |
