| 95e0b96d84b4 ("drm/amd/display: Update HDMI hang w/a to apply to all TMDS signals") |
| 9ae1b27f31d0 ("drm/amd/display: fix hotplug during display off") |
| 7f7652ee8c8c ("drm/amd/display: enable single dp seamless boot") |
| 4edb6fc91878 ("drm/amd/display: Add Renoir clock manager") |
| e7f2c80cbaab ("drm/amd/display: check hpd before retry verify link cap") |
| b5b1f4554904 ("drm/amd/display: Enable type C hotplug") |
| 5ec43eda8550 ("drm/amd/display: enabling seamless boot sequence for dcn2") |
| 8a31820b1218 ("drm/amd/display: Make init_hw and init_pipes generic for seamless boot") |
| 9adc8050bf3c ("drm/amd/display: make firmware info only load once during dc_bios create") |
| ac42fd639550 ("drm/amd/display: reset hdmi tmds rate and data scramble on pipe reset") |
| d3b9f39d8417 ("drm/amdgpu/display: fix the build without CONFIG_DRM_AMD_DC_DSC_SUPPORT") |
| 057fc695e934 ("drm/amd/display: support "dummy pstate"") |
| dcbb45b6eeed ("drm/amd/display: do not read link setting if edp not connected") |
| f591344e89dc ("drm/amd/display: Clean up dynamic metadata logic") |
| 925f566cb7ae ("drm/amd/display: add set and get clock for testing purposes") |
| c43f89f81cc0 ("drm/amd/display: put back front end initialization sequence") |
| 75c35000235f ("drm/amd/display: Power-gate all DSCs at driver init time") |
| 24f1d1cee2bc ("drm/amd/display: Check for valid stream_encode") |
| 6de202373bf6 ("drm/amd/display: move bw calc code into helpers") |
| e0a6440a2961 ("drm/amd/display: Add ability to set preferred link training parameters.") |
| 93c25fbdc30a ("drm/amd/display: initialize p_state to proper value") |
| 41a5a2a8531f ("drm/amd/display: init res_pool dccg_ref, dchub_ref with xtalin_freq") |
| 709527c77a89 ("drm/amd/display: update infoframe after dig fe is turned on (v2)") |
| 170a2398d2d8 ("drm/amd/display: make clk_mgr call enable_pme_wa") |
| 7a5ab155d34a ("drm/amd/display: expose dentist_get_did_from_divider") |
| 1a7d296d162e ("drm/amd/display: Add Underflow Asserts to dc") |
| a6465d1f3b8f ("drm/amd/display: dcn2 use fixed clocks.") |
| 6e17b5b8a846 ("drm/amd/display: update DCN2 uclk switch time") |
| 043f5bb630c1 ("drm/amd/display: Use macro for invalid OPP ID") |
| a746a2585542 ("drm/amd/display: Drive-by fixes for display_mode_vba") |
| ed07237c0c48 ("drm/amd/display: Fix LB BPP and Cursor width") |
| 040a4d63bde4 ("drm/amd/display: DCHUB requestors numbers for Navi.") |
| 4850ce697f98 ("drm/amd/display: Add hubp_init entry to hubp vtable") |
| 42351c66aedc ("drm/amd/display: Add profiling tools for bandwidth validation") |
| 254eb07cb090 ("drm/amd/display: Optimize bandwidth validation by adding early return") |
| 776c1f569f94 ("drm/amd/display: Properly guard display_mode_vba with DCN2") |
| 8e27a2d4cd76 ("drm/amd/display: Fix DCFCLK and SOCCLK not set") |
| 0ba37b20ef1c ("drm/amd/display: fix dsc validation") |
| 00999d991fde ("drm/amd/display: clean up validation failure log spam") |
| 4e0cbbbfbc37 ("drm/amd/display: Clean up locking in dcn*_apply_ctx_for_surface()") |
| 6ba117404e41 ("drm/amd/display: fix pstate allow handling in dcn2") |
| c69dd2d06cdf ("drm/amd/display: Refactor clk_mgr functions") |
| 45021f8ea536 ("drm/amd/display: do not power on eDP power rail early") |
| 98b5b65eb8b7 ("drm/amd/display: disable PSR/ABM before destroy DMCU struct") |
| ae8f425840cb ("drm/amd/display: Ensure DRR triggers in BP") |
| 284358f2acc1 ("drm/amd/display/dc: fix azalia workaround sw implementation bug") |
| 3972c3508594 ("drm/amd/display: Program VTG params after programming Global Sync for DCN2") |
| 97bda0322b8a ("drm/amd/display: Add DSC support for Navi (v2)") |
| 476e955dd679 ("drm/amd/display: Hook DCN2 into amdgpu_dm and expose as config (v2)") |
| e249428256e2 ("drm/amd/display: updates for dcn20_update_bandwidth") |
