| 34a77b0b7b86 ("drm/i915: Add Wa_1605460711 / Wa_1408767742 to ICL and EHL") |
| fb899dd8ea9c ("drm/i915: Apply Wa_1406680159:icl,ehl as an engine workaround") |
| dbe748cd3af4 ("drm/i915/tgl: Don't treat unslice registers as masked") |
| 50148a25f841 ("drm/i915/tgl: Move and restrict Wa_1408615072") |
| 3551ff928744 ("drm/i915/gen11: Moving WAs to rcs_engine_wa_init()") |
| 52c2e4e6f12c ("drm/i915/tgl: Add Wa_1409085225, Wa_14010229206") |
| 3873fd1a43c7 ("drm/i915: Use engine wa list for Wa_1607090982") |
| 561db8296d8b ("drm/i915: Disable tesselation clock gating on tgl A0") |
| 6f4194c8771f ("drm/i915: add Wa_14010594013: icl,ehl") |
| 1cd21a7c5679 ("drm/i915: Add Wa_1407352427:icl,ehl") |
| 4ca153827f65 ("drm/i915/tgl: Extend Wa_1408615072 to tgl") |
| b9cf9dac3dac ("drm/i915: Add Wa_1408615072 and Wa_1407596294 to icl,ehl") |
| ff690b2111ba ("drm/i915/tgl: Implement Wa_1604555607") |
| 5ba2bb587d89 ("drm/i915/tgl: Wa_1606679103") |
| 99db8c59e056 ("drm/i915/tgl: Wa_1607030317, Wa_1607186500, Wa_1607297627") |
| 79bfa607e60f ("drm/i915/tgl: Wa_1607138336") |
| 99739f9431f9 ("drm/i915/tgl: Keep FF dop clock enabled for A0") |
| e5de91e68c5c ("Revert "drm/i915/tgl: Implement Wa_1406941453"") |
| 7f0cc34b5349 ("drm/i915/tgl: Implement Wa_1406941453") |
| 1c757497096f ("drm/i915/tgl: Implement Wa_1409142259") |
| 5d86923060fc ("drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating") |
| 13e53c5c5337 ("drm/i915/tgl: Introduce initial Tiger Lake workarounds") |
| b83a309a9889 ("drm/i915/icl: Add Wa_1409178092") |
| f9a393875d3a ("drm/i915: Disable SAMPLER_STATE prefetching on all Gen11 steppings.") |
| ebd2de47a19f ("drm/i915: Support whitelist workarounds on all engines") |
| fde938867b92 ("drm/i915/selftests: Verify context workarounds") |
| 11334c6aad95 ("drm/i915: Split engine setup/init into two phases") |
| fa9f668141f4 ("drm/i915: Export intel_context_instance()") |
| 251d46b0875c ("drm/i915/gvt: Pin the per-engine GVT shadow contexts") |
| b226c3491b28 ("Merge drm/drm-next into drm-intel-next-queued") |
