| 4d89adc7b56f ("drm/i915/display/dsi: Add support to pipe D") |
| bb747fa5a9cb ("drm/i915/display: Fix TRANS_DDI_MST_TRANSPORT_SELECT definition") |
| b3545e086877 ("drm/i915/tgl: add support to one DP-MST stream") |
| 05f2f03dd206 ("drm/i915/icl: Define missing bitfield for shortplug reg") |
| ab8411483a3e ("drm/i915/icl: Get HW state for DSI encoder") |
| 8327af281d29 ("drm/i915/icl: Add get config functionality for DSI") |
| e27580487321 ("drm/i915/icl: Allocate DSI encoder/connector") |
| 70332ac539c5 ("drm/i915/icl+: Sanitize port to PLL mapping") |
| bf4d57ff4110 ("drm/i915/icl: Find DSI presence for ICL") |
| 4769b598b943 ("drm/i915/icl: Put DSI link in ULPS") |
| 522cc3f717ac ("drm/i915/icl: Power down DSI panel") |
| 4e123bd3039d ("drm/i915/icl: Disable DSI transcoders") |
| d9d996b6ca43 ("drm/i915/icl: Turn OFF panel backlight") |
| c2661638e886 ("drm/i915/icl: Power on DSI panel") |
| bfee32bfca82 ("drm/i915/icl: Set max return packet size for DSI panel") |
| 303e347cebc3 ("drm/i915/icl: Enable DSI transcoders") |
| d1aeb5f399d9 ("drm/i915/icl: Configure DSI transcoder timings") |
| 70f4f502c47e ("drm/i915/icl: Program TRANS_DDI_FUNC_CTL registers") |
| d364dc66e2d5 ("drm/i915/icl: Configure DSI transcoders") |
| ca8fc99f2ac1 ("drm/i915/icl: Get DSI transcoder for a given port") |
| 5fea8645585f ("drm/i915/icl: Program TA_TIMING_PARAM registers") |
| e72cce531017 ("drm/i915/icl: Program DSI clock and data lane timing params") |
| 67551a703544 ("drm/i915/dsi: abstract dphy parameter init") |
| 2bf3f59daeee ("drm/i915/dsi: refactor bitrate calculations in intel_dsi_vbt_init()") |
| 70a7b83628fa ("drm/i915/icl: Program T_INIT_MASTER registers") |
| ba3df888be90 ("drm/i915/icl: Enable DDI Buffer") |
| 3f4b9d9d02c6 ("drm/i915/icl: DSI vswing programming sequence") |
| fc41001d9708 ("drm/i915/icl: Configure lane sequencing of combo phy transmitter") |
| 45f09f7adc8a ("drm/i915/icl: Power down unused DSI lanes") |
| b1cb21a5f1c6 ("drm/i915/icl: Enable DSI IO power") |
| fcfe0bdcb191 ("drm/i915/icl: Program DSI Escape clock Divider") |
| ca3589c11815 ("drm/i915/dsi: rename the current DSI files based on first platform") |
| 27efd2566cb8 ("drm/i915/icl: Define register for DSI PLL") |
| 3160422251b2 ("drm/i915/icp: Add Interrupt Support") |
| 121e758ee578 ("drm/i915/icl: Support for TC North Display interrupts") |
| df0d28c185ad ("drm/i915/icl: GSE interrupt moves from DE_MISC to GU_MISC") |
| 5ee8ee86c86f ("drm/i915/i915_reg.h: fix the checkpatch SPACING issues") |
| 2edd53272120 ("drm/i915/dp: Add support for HBR3 and TPS4 during link training") |
| 00c92d929ac3 ("drm/i915/icl: unconditionally init DDI for every port") |
| b99b9ec1d374 ("drm/i915: Clean up cursor defines") |
| eade6c894498 ("drm/i915: Have plane->get_hw_state() return the current pipe") |
| d6cae4aa30ce ("drm/i915: Call intel_opregion_notify_encoder in intel_sanitize_encoder, v2.") |
| 77312ae8f071 ("drm/i915/psr: vbt change for psr") |
| c894d63c6b36 ("drm/i915/icl: Disable pipe CSC and gamma in cursor plane") |
| 59b74c497ae4 ("drm/i915: Clean up DP pipe select bits") |
| f67dc6d8869f ("drm/i915: Parametrize TRANS_DP_PORT_SEL") |
| b752e995829e ("drm/i915: Check for IVB instead of gen7 when we think about IVB CPU eDP") |
| 762034675ee7 ("drm/i915: Clean up SDVO pipe select bits") |
| a44628b9293b ("drm/i915: Clean up LVDS pipe select bits") |
| 6102a8ee8ad6 ("drm/i915: Clean up ADPA pipe select bits") |
