| 602ae8355056 ("drm/i915: Sanitize VLV/CHV watermarks properly") |
| ff32c54ef1ce ("drm/i915: Compute vlv/chv wms the atomic way") |
| 5012e604891a ("drm/i915: Compute VLV/CHV FIFO sizes based on the PM2 watermarks") |
| 814e7f0bf7b7 ("drm/i915: Plop vlv/chv fifo sizes into crtc state") |
| 855c79f5212a ("drm/i915: Plop vlv wm state into crtc_state") |
| 7eb4941f048f ("drm/i915: Move vlv wms from crtc->wm_state to crtc->wm.active.vlv") |
| f07d43d2da1c ("drm/i915: Track plane fifo sizes under intel_crtc") |
| 75ccb2ecb8fc ("drm/i915: Call the sync_hw hook for power wells without a domain") |
| d8fc70b7367b ("drm/i915: Make power domain masks 64 bit long") |
| 7ff89ca21358 ("drm/i915: Move most cdclk/rawclk related code to intel_cdclk.c") |
| 4717e8bb7341 ("drm/i915: Clean up the .get_cdclk() assignment if ladder") |
| c49a0d054a05 ("drm/i915: s/get_display_clock_speed/get_cdclk/") |
| 4e841ecd4e18 ("drm/i915: Nuke intel_mode_max_pixclk()") |
| a7d1b3f41a2d ("drm/i915: Store the pipe pixel rate in the crtc state") |
| 3c779a49bd7c ("drm/i915: Avoid BIT(max) - 1 and use GENMASK(max - 1, 0)") |
| 6248017ae530 ("drm/i915: Get correct display clock on 945gm") |
| b976dc53ec43 ("drm/i915: Introduce IS_GEN9_BC for Skylake and Kabylake.") |
| 8da53efaa228 ("drm/i915/kbl: Apply WaIncreaseDefaultTLBEntries on KBL.") |
| 31bb2ef97ea9 ("drm/i915: Check for NULL atomic state in intel_crtc_disable_noatomic()") |
| a8cd6da0c0d5 ("drm/i915: Remove crtc->config usage from intel_modeset_readout_hw_state()") |
| 1d4258db3e0b ("drm/i915: Remove useless casts to intel_plane_state") |
| ef426c103892 ("Merge tag 'drm-misc-next-2016-12-30' of git://anongit.freedesktop.org/git/drm-misc into drm-intel-next-queued") |
