| 8199e49ff1f6 ("ARM: dts: r8a77(43|9[013]): Add missing OPP properties for CPUs") |
| a60ddf507dda ("ARM: dts: r8a7743: Add missing clock for secondary CA15 CPU core") |
| 5bdc81259bb0 ("ARM: dts: r8a7790: add cpu capacity-dmips-mhz information") |
| 362b334b1794 ("ARM: dts: r8a7791: Convert to new CPG/MSSR bindings") |
| d77fe9537688 ("ARM: dts: r8a7793: Convert to new CPG/MSSR bindings") |
| 5802c4206365 ("ARM: dts: r8a7790: Convert to new CPG/MSSR bindings") |
| 60dce695b097 ("ARM: dts: r8a7743: Add APMU node and second CPU core") |
| e15ebbfa1feb ("ARM: dts: r8a7791: Add GyroADC clock and device node") |
| 1cd9028027c7 ("ARM: dts: r8a7793: Correct parent of SSI[0-9] clocks") |
| 16fe68dcab57 ("ARM: dts: r8a7791: Correct parent of SSI[0-9] clocks") |
| d13d4e063d4a ("ARM: dts: r8a7790: Correct parent of SSI[0-9] clocks") |
| 2f25c2d1cdf0 ("ARM: dts: r8a7793: Add INTC-SYS clock to device tree") |
| c2f2e266acb3 ("ARM: dts: r8a7791: Add INTC-SYS clock to device tree") |
| 9e58523624fc ("ARM: dts: r8a7790: Add INTC-SYS clock to device tree") |
| 37f0c804e57a ("ARM: dts: r8a7743: Remove unit-address and reg from integrated cache") |
| 34e8d993a68a ("ARM: dts: r8a7743: initial SoC device tree") |
| 06b64afa6e98 ("ARM: dts: r8a7793: Enable VIN0-VIN2") |
