| 9e953cda5cdf ("riscv: Introduce huge page support for 32/64bit kernel") |
| a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs") |
| f6635f873a60 ("riscv: move switch_mm to its own file") |
| a3182c91ef4e ("RISC-V: Access CSRs using CSR numbers") |
| df16c40cbfb4 ("riscv: clear all pending interrupts when booting") |
| 2353ecc6f91f ("bpf, riscv: add BPF JIT for RV64G") |
| 94f592f0e5b9 ("RISC-V: Add the directive for alignment of stvec's value") |
| 6a4d4b3253c1 ("Merge tag 'riscv-for-linus-4.18-merge_window' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux") |
