| be8a4b2d3199 ("drm/i915: Add debugs for the C8 vs. legacy LUT case") |
| e0510da05192 ("drm/i915: Extract check_luts()") |
| 5a0404408d32 ("drm/i915: Fix legacy gamma mode for ICL") |
| f19d90eed648 ("drm/i915: Split ilk vs. icl csc matrix handling") |
| b281264f8b81 ("drm/i915: Clean the csc limited range/identity programming") |
| c9e235aa0f9d ("drm/i915: Extract ilk_csc_convert_ctm()") |
| d2c19b06d6ea ("drm/i915: Clean up ilk/icl pipe/output CSC programming") |
| 386ba08fb595 ("drm/i915: Extract ilk_csc_limited_range()") |
| 9fdfb8e7308b ("drm/i915: Precompute/readout/check CHV CGM mode") |
| a1f1e61bfb0a ("drm/i915: Readout and check csc_mode") |
| a91de580541c ("drm/i915/icl: Enable pipe output csc") |
| 255fcfbc3c18 ("drm/i915/icl: Enable ICL Pipe CSC block") |
| 13717cef4c1d ("drm/i915/icl: Add icl pipe degamma and gamma support") |
| 02c52f1ed20a ("drm/i915: Disable pipe gamma when C8 pixel format is used") |
| 0593d2cd3813 ("drm/i915: Turn off pipe CSC when it's not needed") |
| 0fc3f8e7540f ("drm/i915: Turn off pipe gamma when it's not needed") |
| 8271b2ef71aa ("drm/i915: Track pipe csc enable in crtc state") |
| 5f29ab23046a ("drm/i915: Track pipe gamma enable/disable in crtc state") |
| 9d5441de28e2 ("drm/i915: Populate gamma_mode for all platforms") |
| 051a6d8d3ca0 ("drm/i915: Move LUT programming to happen after vblank waits") |
| 4d8ed54c0447 ("drm/i915: Split color mgmt based on single vs. double buffered registers") |
| 87cefd57c88a ("drm/i915: Pull GAMMA_MODE write out from haswell_load_luts()") |
| 23b03a272c2b ("drm/i915: Constify the state arguments to the color management stuff") |
| 5f4f3e386b36 ("drm/i915: Precompute gamma_mode") |
| 7eb31a0bb2c1 ("drm/i915: Split the gamma/csc enable bits from the plane_ctl() function") |
| 108d14bdaef6 ("drm/i915: Setup PIPE_CHICKEN for fastsets too") |
| e4c0d5314ded ("drm/i915: Apply LUT validation checks to platforms more accurately (v3)") |
| c0550305fcbd ("drm/i915: Force background color to black for gen9+ (v2)") |
| 790cc9941b13 ("drm/i915: Clean up intel_plane_atomic_check_with_state()") |
| 85e2d61e4976 ("drm/i915: Validate userspace-provided color management LUT's (v4)") |
| 129fe7516b23 ("drm/i915/color: switch to kernel types") |
| c4aa2eca319c ("drm/i915/sprite: switch to kernel types") |
| 0258404f9d38 ("drm/i915: start moving runtime device info to a separate struct") |
| 167bc759e823 ("drm/i915: Restrict PSMI context load w/a to Haswell GT1") |
| a489334941d4 ("drm/i915: Fix Cherryview oops on boot") |
| f513ac76530c ("drm/i915/icl: Mind the SFC units when resetting VD or VEBox engines") |
| 57b19d55189b ("drm/i915/icl: Record the valid VDBoxes with SFC capability") |
| cf819eff907a ("drm/i915: replace IS_GEN<N> with IS_GEN(..., N)") |
| 302da0cdf784 ("drm/i915: Use intel_ types more consistently for color management code (v2)") |
| d15f9cdd59ba ("drm/i915/icl: Do not change reserved registers related to PSR2") |
| 517974992593 ("drm/i915: Allocate a common scratch page") |
| 452420d22d5b ("drm/i915: Fuse per-context workaround handling with the common framework") |
| 69bcdecf1af5 ("drm/i915: Move register white-listing to the common workaround framework") |
| 28d6ccce73be ("drm/i915/selftests: Add tests for GT and engine workaround verification") |
| 094304beb4e1 ("drm/i915: Verify GT workaround state after GPU init") |
| 4a15c75c4246 ("drm/i915: Introduce per-engine workarounds") |
| 25d140faaa25 ("drm/i915: Record GT workarounds in a list") |
| e1bf094b3c75 ("drm/i915: Add HAS_DISPLAY() and use it") |
| b9f78d675230 ("drm/i915/selftests: Fix live_workarounds to actually do resets") |
| 8d2f6e2f2721 ("drm/i915/selftests: Extract spinner code") |
