| edb2e5301c44 ("drm/i915: Track whether the DP link is trained or not") |
| c85d200e8321 ("drm/i915: Move SST DP link retraining into the ->post_hotplug() hook") |
| dba14b27dd3c ("drm/i915: Reinitialize sink scrambling/TMDS clock ratio on HPD") |
| 20f24d776d1b ("drm/i915: Implement HDCP for DisplayPort") |
| 42e5e6576526 ("drm/i915: sync dp link status checks against atomic commmits") |
| 2f7734770cfb ("drm/i915: Clean up DP code local variables and calling conventions") |
| 8f4f27970723 ("drm/i915: Nuke intel_digital_port->port") |
| adc103047e58 ("drm/i915: Eliminate some encoder->crtc usage from DP code") |
| 7e732cacb1ae ("drm/i915: Stop frobbing with DDI encoder->type") |
| 436009b578ab ("drm/i915/cnl: Force DDI_A_4_LANES when needed.") |
| 081dfcfafcbb ("drm/i915: Pass the encoder type explicitly to skl_set_iboost()") |
| 975786ee0e25 ("drm/i915: Extract intel_ddi_get_buf_trans_hdmi()") |
| d8fe2c7f3365 ("drm/i915: Relocate intel_ddi_get_buf_trans_*() functions") |
| 1210d3889077 ("drm/i915: Use bdw_ddi_translations_fdi for Broadwell") |
| 40b2be419f8a ("drm/i915: Dump 'output_types' in crtc state dump") |
| c5ce4ef3282b ("drm/i915/crt: clean up encoder hook assignment") |
| 364a3fe18235 ("drm/i915: push DDI and DSI underrun reporting on enable to encoder") |
| 51c4fa6903f9 ("drm/i915: push DDI CRT underrun reporting on enable to encoder") |
| 83482ca3b4fe ("drm/i915: avoid potential uninitialized variable use") |
| ed69cd40685c ("drm/i915/glk, cnl: Implement WaDisableScalarClockGating") |
| 3bc31a7f4d37 ("drm/i915/dp: Remove useless debug about TPS3 support") |
| 1a8ff6076e8f ("drm/i915: Reorganize .disable hooks for pre-DDI DP") |
| 76a4b41d654c ("drm/i915: Drop useless HAS_PSR() check") |
| bf5035564579 ("drm/i915/cnl: Fix DDI hdmi level selection.") |
| cf3e0fb48cdb ("drm/i915/cnl: Move ddi buf trans related functions up.") |
| cc9cabfdec38 ("drm/i915/cnl: Move voltage check into ddi buf trans functions.") |
| 381f957044d0 ("drm/i915: Enable voltage swing before enabling DDI_BUF_CTL.") |
| 2f7460a75aa4 ("drm/i915: Align vswing sequences with old ddi buffer registers.") |
| d509af6c85bb ("drm/i915: decouple gen9 and gen10 dp signal levels.") |
| 1b6e2fd2896a ("drm/i915: Introduce intel_ddi_dp_level.") |
| d2419ffc10e4 ("drm/i915: Plumb crtc_state to PSR enable/disable") |
| 1853a9daa19e ("drm/i915/dp: make is_edp non-static and rename to intel_dp_is_edp") |
| 7b91bf7f9196 ("drm/i915/dp: rename intel_dp_is_edp to intel_dp_is_port_edp") |
| dc911f5bd8aa ("drm/i915/edp: Allow alternate fixed mode for eDP if available.") |
| 1a92c70ed805 ("drm/i915/dp: Generalize intel_dp_link_params function to accept arguments to be validated") |
| f761bef2f341 ("drm/i915: Introduce intel_hpd_pin function.") |
| 256cfdde42c0 ("drm/i915: Simplify hpd pin to port") |
| d907b6658a7b ("drm/i915/cnl: Add allowed DP rates for Cannonlake.") |
| 50946c89850d ("drm/i915: Return correct EDP voltage swing table for 0.85V") |
| 2901215920aa ("drm/i915: Pass enum pipe to intel_set_pch_fifo_underrun_reporting()") |
| a9701a897067 ("drm/i915/cnl: Get DDI clock based on PLLs.") |
| 93e5f0b65ab8 ("drm/i915: Make intel_digital_port_connected() work for any port") |
| da411a48bdeb ("drm/i915/cfl: Basic DDI plumbing for Coffee Lake.") |
| 0091abc3a621 ("drm/i915/cnl: Enable loadgen_select bit for vswing sequence") |
| cf54ca8bc567 ("drm/i915/cnl: Implement voltage swing sequence.") |
| 83fb7ab404fd ("drm/i915/cnl: Add DDI Buffer translation tables for Cannonlake.") |
| a927c927de34 ("drm/i915/cnl: Initialize PLLs") |
| 555e38d27317 ("drm/i915/cnl: DDI - PLL mapping") |
| d8d4a512a6ff ("drm/i915/cnl: Implement CNL display init/unit sequence") |
| ef4f7a689ac5 ("drm/i915/cnl: Implement .set_cdclk() for CNL") |
