| ed581a0ace44 ("drm/amd/display: wait for update when setting dpg test pattern") |
| b1f6d01c4a3b ("drm/amd/display: re structure odm to allow 4 to 1 support") |
| 4c3cfe14c04e ("Revert "drm/amd/display: add global master update lock for DCN2"") |
| 544618596fd5 ("drm/amd/display: wake up ogam mem pwr before programming ocsc") |
| 2b162fd30249 ("drm/amd/display: update optc odm interface for more than 2 opps") |
| c681491a0921 ("drm/amd/display: fix pipe selection logic in validate") |
| 1a9e3d4569fc ("drm/amd/display: Set DSC before DIG front-end is connected to its back-end") |
| 606b355170b5 ("drm/amd/display: add hdmi2.1 dsc pps packet programming") |
| 6de202373bf6 ("drm/amd/display: move bw calc code into helpers") |
| ec16ac6b4264 ("drm/amd/display: fix dsc disable") |
| a6465d1f3b8f ("drm/amd/display: dcn2 use fixed clocks.") |
| f82c916c4197 ("drm/amd/display: add some parameters to validate bandwidth functions") |
| ba32c50f0446 ("drm/amd/display: decouple dsc adjustment out of enablement") |
| 278141f58e2c ("drm/amd/display: Use DCN2 functions instead of DCE") |
| 6936c8b1d415 ("drm/amd/display: DCN2 Engine-specifc encoder allocation") |
| 324707fdf83a ("drm/amd/display: Set test pattern on blank when using Visual Confirm") |
| ed07237c0c48 ("drm/amd/display: Fix LB BPP and Cursor width") |
| fbc9ca671f4f ("drm/amd/display: Fix ODM combine data format") |
| c9ae6e1691cd ("drm/amd/display: Acquire DSC HW resource only if required by stream") |
| 6c5be4ac6308 ("drm/amd/display: add global master update lock for DCN2") |
| 42351c66aedc ("drm/amd/display: Add profiling tools for bandwidth validation") |
| 254eb07cb090 ("drm/amd/display: Optimize bandwidth validation by adding early return") |
| ede37e4ce495 ("drm/amd/display: fix can not turn on two displays due to DSC_RESOURCE failed.") |
| 8e27a2d4cd76 ("drm/amd/display: Fix DCFCLK and SOCCLK not set") |
| db5378c1dcff ("drm/amd/display: isolate global double buffer lock programming") |
| 0ba37b20ef1c ("drm/amd/display: fix dsc validation") |
| 00999d991fde ("drm/amd/display: clean up validation failure log spam") |
| c69dd2d06cdf ("drm/amd/display: Refactor clk_mgr functions") |
| ae8f425840cb ("drm/amd/display: Ensure DRR triggers in BP") |
| 3972c3508594 ("drm/amd/display: Program VTG params after programming Global Sync for DCN2") |
| 97bda0322b8a ("drm/amd/display: Add DSC support for Navi (v2)") |
| 476e955dd679 ("drm/amd/display: Hook DCN2 into amdgpu_dm and expose as config (v2)") |
| e249428256e2 ("drm/amd/display: updates for dcn20_update_bandwidth") |
| cb0b554abeac ("drm/amd/display: add fast_validate parameter to dcn20_validate_bandwidth") |
| 6fbefb84a98e ("drm/amd/display: Add DC core changes for DCN2") |
| 7ed4e6352c16 ("drm/amd/display: Add DCN2 HW Sequencer and Resource") |
| 345429a67c48 ("drm/amd/display: Add DCN2 DWB") |
| f7de96ee8b5f ("drm/amd/display: Add DCN2 DPP") |
| f789b0b82bf0 ("drm/amd/display: Add DCN2 MPC") |
| 2d78b3a177fe ("drm/amd/display: Add DCN2 OPTC") |
| fcee01b9f82d ("drm/amd/display: Add DCN2 clk mgr") |
| ca4d9b3a5a3b ("drm/amd/display: Add DCN2 DIO") |
| 728c06986a4f ("drm/amd/display: Add DCN2 changes to DML") |
| 48321c3dde79 ("drm/amd/display: Read soc_bounding_box from gpu_info (v2)") |
| 35c2e91059cb ("drm/amdgpu: parse the new members added by gpu_info ucode v1_1") |
| 109c80ddb40f ("drm/amdgpu: add gpu_info_firmware v1_1 structure for navi10") |
| c5c07cb5435e ("drm/amd/display: Refactor DIO stream encoder") |
| baa1fd7f32f2 ("drm/amd/display: Refactor clk_mgr functions") |
| 961ea20155d7 ("drm/amd/display: Fix type of pp_smu_wm_set_range struct") |
| 9b93eb475aa9 ("drm/amd/display: move clk_mgr files to right place") |
