| 796ef2eff3cc ("drm/i915/gt: Avoid multi-LRI on Sandybridge") |
| 902eb748e5c3 ("drm/i915/gt: Tidy up full-ppgtt on Ivybridge") |
| d63411000741 ("drm/i915/gt: Turn vm off then on again for gen7 mm switch") |
| 0471a44871cf ("drm/i915/gt: Bump the PP_DIR invalidation for Baytrail") |
| 13bb5b99eca0 ("drm/i915/gt: Set the PD again for Haswell") |
| f70de8d2ca6b ("drm/i915/gt: Track the context validity explicitly") |
| 1bbdd241ffeb ("drm/i915: Refactor gen6_flush_pd()") |
| f997056d5b17 ("drm/i915/gt: Push the flush_pd before the set-context") |
| 3cd6e8860ecd ("drm/i915/gen7: Re-enable full-ppgtt for ivb & hsw") |
| 7dc56af5260e ("drm/i915/selftests: Verify the LRC register layout between init and HW") |
| c8185520aed6 ("drm/i915/gtt: Make sure the gen6 ppgtt is bound before first use") |
| 5bf05dc58d65 ("drm/i915/tgl: Register state context definition for Gen12") |
| cdb736fa8b8b ("drm/i915: Use engine relative LRIs on context setup") |
| c1d143dd2ac8 ("drm/i915: Remove ppgtt->dirty_engines") |
| 0b718ba1e884 ("drm/i915/gtt: Downgrade Cherryview back to aliasing-ppgtt") |
| 3dc007fe9b2b ("drm/i915/gtt: Downgrade gen7 (ivb, byt, hsw) back to aliasing-ppgtt") |
| 529880098431 ("drm/i915: to make vgpu ppgtt notificaiton as atomic operation") |
| eaef5b3c4113 ("drm/i915: Refactor instdone loops on new subslice functions") |
