| 3c23ed13112c ("drm/i915: Fix the pipe state timing mismatch warnings") |
| 8327af281d29 ("drm/i915/icl: Add get config functionality for DSI") |
| e27580487321 ("drm/i915/icl: Allocate DSI encoder/connector") |
| 70332ac539c5 ("drm/i915/icl+: Sanitize port to PLL mapping") |
| bf4d57ff4110 ("drm/i915/icl: Find DSI presence for ICL") |
| 4769b598b943 ("drm/i915/icl: Put DSI link in ULPS") |
| 522cc3f717ac ("drm/i915/icl: Power down DSI panel") |
| 4e123bd3039d ("drm/i915/icl: Disable DSI transcoders") |
| d9d996b6ca43 ("drm/i915/icl: Turn OFF panel backlight") |
| bfee32bfca82 ("drm/i915/icl: Set max return packet size for DSI panel") |
| d1aeb5f399d9 ("drm/i915/icl: Configure DSI transcoder timings") |
| 70f4f502c47e ("drm/i915/icl: Program TRANS_DDI_FUNC_CTL registers") |
| d364dc66e2d5 ("drm/i915/icl: Configure DSI transcoders") |
| ca8fc99f2ac1 ("drm/i915/icl: Get DSI transcoder for a given port") |
| 67551a703544 ("drm/i915/dsi: abstract dphy parameter init") |
| 2bf3f59daeee ("drm/i915/dsi: refactor bitrate calculations in intel_dsi_vbt_init()") |
| 70a7b83628fa ("drm/i915/icl: Program T_INIT_MASTER registers") |
| ba3df888be90 ("drm/i915/icl: Enable DDI Buffer") |
| 3f4b9d9d02c6 ("drm/i915/icl: DSI vswing programming sequence") |
| fc41001d9708 ("drm/i915/icl: Configure lane sequencing of combo phy transmitter") |
| 45f09f7adc8a ("drm/i915/icl: Power down unused DSI lanes") |
| b1cb21a5f1c6 ("drm/i915/icl: Enable DSI IO power") |
| fcfe0bdcb191 ("drm/i915/icl: Program DSI Escape clock Divider") |
| ca3589c11815 ("drm/i915/dsi: rename the current DSI files based on first platform") |
| 27efd2566cb8 ("drm/i915/icl: Define register for DSI PLL") |
| 00c92d929ac3 ("drm/i915/icl: unconditionally init DDI for every port") |
| d6cae4aa30ce ("drm/i915: Call intel_opregion_notify_encoder in intel_sanitize_encoder, v2.") |
| c27e917e2bda ("drm/i915/icl: add basic support for the ICL clocks") |
| 2320175feb74 ("drm/i915: Implement HDCP for HDMI") |
| 09a28bd9e802 ("drm/i915: Move display related definitions to dedicated header") |
| b74eeeb6b1ab ("drm/i915: Move some utility functions to i915_util.h") |
| 8edcda1266f9 ("drm/i915: Protect DDI port to DPLL map from theoretical race.") |
| b68763741aa2 ("drm/i915: Restore GT performance in headless mode with DMC loaded") |
| 6a44e1772177 ("drm/i915: remove stale comment from sanitize_encoder") |
| dd57602efbce ("drm/i915: Switch fbc over to for_each_new_intel_plane_in_state()") |
| ed15030d7ab0 ("drm/i915: s/enum plane/enum i9xx_plane_id/") |
| b1e01595a66d ("drm/i915: Redo plane sanitation during readout") |
| 51f5a0963984 ("drm/i915: Add .get_hw_state() method for planes") |
| 2952cd6fb4cc ("drm/i915: Let's use more enum intel_dpll_id pll_id.") |
| 31d1d3c8862e ("drm/i915: adjust get_crtc_fence_y_offset() to use base.y instead of crtc.y") |
| 779d4d8f083e ("drm/i915: Unify skylake plane disable") |
| 9a8cc576002a ("drm/i915: Unify skylake plane update") |
| e288881b08dc ("drm/i915: dspaddr_offset doesn't need to be more than local variable") |
| bf0a5d4b223d ("drm/i915: move adjusted_x/y from crtc to cache.") |
| 6b8506d575e3 ("drm/i915: Extract intel_ddi_clk_disable()") |
| 2de3813880bf ("drm/i915: add the BXT and CNL DPLL registers to pipe_config_compare") |
| 7c26240e8a19 ("drm/i915: Try harder to finish the idle-worker") |
| 3daa3cee6ebc ("drm/i915: push DDI CRT underrun reporting on disable to encoder") |
| 51c4fa6903f9 ("drm/i915: push DDI CRT underrun reporting on enable to encoder") |
| ed69cd40685c ("drm/i915/glk, cnl: Implement WaDisableScalarClockGating") |
