| fc03acaeab35 ("irqchip/irq-sifive-plic: Check and continue in case of an invalid cpuid.") |
| f99fb607fb2b ("RISC-V: Use Linux logical CPU number instead of hartid") |
| 6825c7a80f18 ("RISC-V: Add logical CPU indexing for RISC-V") |
| a37d56fc4011 ("RISC-V: Use WRITE_ONCE instead of direct access") |
| 177fae451588 ("RISC-V: Rename im_okay_therefore_i_am to found_boot_cpu") |
| b2f8cfa7ac34 ("RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartid") |
| 19ccf29bb18f ("RISC-V: Filter ISA and MMU values in cpuinfo") |
| 8237f8bc4f6e ("irqchip: add a SiFive PLIC driver") |
| 62b019436814 ("clocksource: new RISC-V SBI timer driver") |
| 6ea0f26a7913 ("RISC-V: implement low-level interrupt handling") |
| b9490350f751 ("RISC-V: remove timer leftovers") |
| 8606544890d7 ("RISC-V: Don't include irq-riscv-intc.h") |
| 2861ae302f6b ("riscv: use NULL instead of a plain 0") |
| 527cd2077188 ("Merge tag 'riscv-for-linus-4.17-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux") |
