| c652923afa7c ("drm/amdgpu: enable xgmi support for sienna cichlid") |
| c1299461b7d6 ("drm/amdgpu: request init data in virt detection") |
| 5278a159cf35 ("drm/amdgpu: support reserve bad page for virt (v3)") |
| 95a2f917387a ("drm/amdgpu: restrict debugfs register access under SR-IOV") |
| 122078de168b ("drm/amdgpu: equip new req_init_data handshake") |
| aa53bc2edb66 ("drm/amdgpu: introduce new request and its function") |
| 3aa0115d238c ("drm/amdgpu: cleanup all virtualization detection routine") |
| a9ffe2a98338 ("drm/amdgpu/debugfs: properly handle runtime pm") |
| c9ffa427db34 ("drm/amd/powerplay: enable pp one vf mode for vega10") |
| 474b6d296f23 ("drm/amdgpu: enable JPEG2.0 dpm") |
| 6ac27241106b ("drm/amdgpu: add JPEG v2.0 function supports") |
| bb0db70f3f75 ("drm/amdgpu: separate JPEG1.0 code out from VCN1.0") |
| 9d9cc9b8fe85 ("drm/amdgpu: add amdgpu_jpeg and JPEG tests") |
| 88a1c40a04de ("drm/amdgpu: add JPEG HW IP and SW structures") |
| a28fda312a9f ("drm/amdgpu: Avoid accidental thread reactivation.") |
| 923c087a1f1e ("drm/amdgpu: Add the HDP flush support for Navi") |
| b05b69036f74 ("drm/amdgpu: For Navi12 SRIOV VF, register mailbox functions") |
| 3636169cc0e1 ("drm/amdgpu: Add SRIOV mailbox backend for Navi1x") |
| bebc07628545 ("drm/amdgpu: switch to new amdgpu_nbio structure") |
| 078ef4e93250 ("drm/amdgpu: add new amdgpu nbio header file") |
| 6892c1f866bf ("drm/amdgpu: remove set but not used variable 'psp_enabled'") |
| f78e007f76bd ("drm/amdgpu: enable clock gating for renoir") |
| f60481a94529 ("drm/amdgpu: add gfx clock gating for Arcturus") |
| b5c73856408b ("drm/amdgpu/discovery: move common discovery code out of navi1*_reg_base_init()") |
| 7e17e58bdde2 ("drm/amdgpu: set nbio/hdp cg for navi12") |
| 03d0a073cf3f ("drm/amdgpu: initialize reg base for navi12") |
| 839f9117e1c2 ("drm/amd/powerplay: guard consistency between CPU copy and local VRAM") |
| 4cd4c5c064bd ("drm/amdgpu: cleanup vega10 SRIOV code path") |
| 4fa1c6a679bb ("drm/amdgpu: add RREG64/WREG64(_PCIE) operations") |
| f0d2a7dc1154 ("drm/amd/powerplay: fix null pointer dereference around dpm state relates") |
| 64671c0fdc91 ("drm/amdgpu: add perfmon and fica atomics for df") |
| 780f3a9c5b9f ("drm/amd/powerplay: some cosmetic fixes") |
| ebf8fc31cbce ("drm/amd/powerplay: custom peak clock freq for navi10") |
| fa739f4b0686 ("drm/amdgpu: add multiple instances support for Arcturus") |
| c01b6a1d3867 ("drm/amdgpu: modify amdgpu_vcn to support multiple instances") |
| 989b6a054997 ("drm/amdgpu: add vcn nbio doorbell range setting for 2nd vcn instance") |
| 530e30fc32d3 ("drm/amdgpu: enable the Doorbell support for VCN2.5") |
| 39a5053fb223 ("drm/amdgpu: add vcn doorbell range function to nbio7.4 (v2)") |
| 800107370810 ("drm/amdgpu/VCN2.5: set JPEG decode ring functions") |
| e87d5a7a23c7 ("drm/amdgpu: add JPEG2.5 HW start and stop") |
| a4767886e5cb ("drm/amdgpu/VCN2.5: set encode ring functions") |
| 185a579700ec ("drm/amdgpu/VCN2.5: set decode ring functions") |
| cbead2bdfcf1 ("drm/amdgpu: add VCN2.5 VCPU start and stop") |
| 28c17d72072b ("drm/amdgpu: add VCN2.5 basic supports") |
| 0e54df05724e ("drm/amdgpu/soc15: add Arcturus common ip blocks") |
| 0fe6a7b49f61 ("drm/amdgpu: support hdp flush for more sdma instances") |
| e78705ec5a7f ("drm/amdgpu: dynamically initialize IP offset for Arcturus") |
| a2d15ed73336 ("drm/amdgpu: rename AMDGPU_GFXHUB/MMHUB macro with hub number") |
| 5e71e011ff84 ("drm/amdgpu/soc15: add support for navi14") |
| c20697674d32 ("drm/amdgpu/discovery: init reg base offset via ip discovery for navi14") |
