| 4ba487019d1a ("drm/i915: Fix WARN_ON condition for cursor plane ddb allocation") |
| 10a7e07b68b9 ("drm/i915: Make sure cursor has enough ddb for the selected wm level") |
| 961d95e09c04 ("drm/i915: Account for minimum ddb allocation restrictions") |
| b19c9bcaa20e ("drm/i915: Fix > vs >= mismatch in watermark/ddb calculations") |
| b52c273be687 ("drm/i915: Don't ignore level 0 lines watermark for glk+") |
| 143c335ad27f ("drm/i915/i915_drv.h: switch to kernel types") |
| 5ce9a6497914 ("drm/i915/pm: switch to kernel types") |
| 0e6e0be4c952 ("drm/i915: Markup paired operations on display power domains") |
| a037121c3c7f ("drm/i915: Mark up debugfs with rpm wakeref tracking") |
| 506d1f62454b ("drm/i915: Track GT wakeref") |
| 16e4dd0342a8 ("drm/i915: Markup paired operations on wakerefs") |
| bd780f37a361 ("drm/i915: Track all held rpm wakerefs") |
| f663b0ca9b7d ("drm/i915/selftests: recreate WA lists inside the selftest") |
| d25f71a162a9 ("drm/i915: Return immediately if trylock fails for direct-reclaim") |
| 0258404f9d38 ("drm/i915: start moving runtime device info to a separate struct") |
| 167bc759e823 ("drm/i915: Restrict PSMI context load w/a to Haswell GT1") |
| 38b3416f3c2f ("drm/i915/bios: Parse the VBT TypeC and Thunderbolt port flags") |
| f513ac76530c ("drm/i915/icl: Mind the SFC units when resetting VD or VEBox engines") |
| 57b19d55189b ("drm/i915/icl: Record the valid VDBoxes with SFC capability") |
| 921f3a60e54e ("drm/i915/selftests: Verify we can perform resets from atomic context") |
| 5edd56d394dc ("drm/i915/selftests: Check we can recover a wedged device") |
| cf819eff907a ("drm/i915: replace IS_GEN<N> with IS_GEN(..., N)") |
| d8e874980241 ("drm/i915: Switch to level-based DDB allocation algorithm (v5)") |
| cd1d3ee90e5e ("drm/i915: Use intel_ types more consistently for watermark code (v2)") |
| 0b5b45a61d3f ("drm/i915: Remove dead update_wm_pre assignment from SKL wm code") |
| 099a132bfb65 ("drm/i915: Use explicit old crtc state in skl_compute_wm()") |
| e6154e4cb8b0 ("drm/i915: Skip the ERR_PTR error state") |
| 3abd6143f971 ("drm/i915/selftests: verify_gt_engine_wa() needs rpm wakeref") |
| d15f9cdd59ba ("drm/i915/icl: Do not change reserved registers related to PSR2") |
| 517974992593 ("drm/i915: Allocate a common scratch page") |
| 452420d22d5b ("drm/i915: Fuse per-context workaround handling with the common framework") |
| 69bcdecf1af5 ("drm/i915: Move register white-listing to the common workaround framework") |
| 28d6ccce73be ("drm/i915/selftests: Add tests for GT and engine workaround verification") |
| 094304beb4e1 ("drm/i915: Verify GT workaround state after GPU init") |
| 4a15c75c4246 ("drm/i915: Introduce per-engine workarounds") |
| 25d140faaa25 ("drm/i915: Record GT workarounds in a list") |
| e1bf094b3c75 ("drm/i915: Add HAS_DISPLAY() and use it") |
| ab8411483a3e ("drm/i915/icl: Get HW state for DSI encoder") |
| 8327af281d29 ("drm/i915/icl: Add get config functionality for DSI") |
| e27580487321 ("drm/i915/icl: Allocate DSI encoder/connector") |
| b9f78d675230 ("drm/i915/selftests: Fix live_workarounds to actually do resets") |
| 8d2f6e2f2721 ("drm/i915/selftests: Extract spinner code") |
| a24c62f94be1 ("drm/i915/dsc: Enable and disable appropriate power wells for VDSC") |
| a600622c09dd ("drm/i915/dp: Disable DSC in source by disabling DSS CTL bits") |
| 7182414e2530 ("drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling") |
| 168243c18010 ("drm/i915/dsc: Define & Compute VESA DSC params") |
| a4a157777c80 ("drm/i915/dp: Compute DSC pipe config in atomic check") |
| ff43bc379e16 ("drm/i915: Move ddb/wm programming into plane update/disable hooks on skl+") |
| 51de9c6d2559 ("drm/i915: Don't pass dev_priv around so much") |
| 8315847bf4df ("drm/i915: Clean up skl+ vs. icl+ watermark computation") |
