| 6c0984d53b07 ("drm/amd/display: Raise dispclk value for dce_update_clocks") |
| fab55d61b9f0 ("drm/amd/display: redesign dce/dcn clock voltage update request") |
| 765b26836430 ("drm/amd/display: replace clocks_value struct with dc_clocks") |
| 5099114ba3b2 ("drm/amdgpu/display: drop DRM_AMD_DC_FBC kconfig option") |
| 1a05873f21d6 ("drm/amd/display: Refactor audio programming") |
| 87ac8fb08bc7 ("drm/amd/display: disable FBC on underlay pipe") |
| 2fa417324abd ("drm/amd/display: Remove PRE_VEGA flag") |
| 6da2b9332c57 ("amdgpu/dm: Default PRE_VEGA ASIC support to 'y'") |
| 17ac50368f83 ("drm/amd/display: clean up dcn pplib notification call") |
| 45bb8dd696ea ("drm/amd/display: Set disp clk in a safe way to avoid over high dpp clk. (v2)") |
| 8e437c799158 ("drm/amd/display: Modified set bandwidth sequence.") |
| 623a7e96cd73 ("drm/amd/display: Remove 300Mhz minimum disp clk limit.") |
| 28d4175413ef ("drm/amd/display: fix dcn1 dppclk when min dispclk patch applies") |
| 1296423bf23c ("drm/amd/display: define DC_LOGGER for logger") |
| 2f3fd67a8af2 ("drm/amd/display: Use MACROS instead of dm_logger") |
| 15cf3974eb06 ("drm/amd/display: add diags clock programming") |
| f553e6810259 ("drm/amd/display: add per pipe dppclk") |
| ea7ea2a8cac1 ("drm/amd/display: fix missing az disable in reset backend") |
| 3d53f424796b ("drm/amd/display: update cur_clock correctly within set bandwidth") |
| fdf0c1c2f75e ("drm/amd/display: Add logging for aux DPCD access") |
| 3e332d3a5a64 ("drm/amd/display: Make FBC work without fbdev emulation") |
| 4cac1e6d2ffa ("drm/amd/display: Keep eDP stream enabled during boot.") |
| 91d4a1290034 ("drm/amd/display: boot up/S4 fix mainlink off before BL.") |
| 25b304471846 ("drm/amd/display: enable #PME code path for RV.") |
| c5fc7f59a71a ("drm/amd/display: resume from S3 bypass power down HW block.") |
| 5180d4a4766d ("drm/amd/display: add eDP 1.2+ polling for T7") |
| f774b3398264 ("drm/amd/display: remove unused function prototypes") |
| 24a30505f312 ("drm/amd/display: Check hubp in pipe_ctx not in res_pool.") |
| 69b9723a81e7 ("drm/amd/display: wait for T9 after backlight off mainlink blank.") |
| ac916c914c31 ("drm/amd/display: Remove return when no EDID read.") |
| 367e66870e9c ("drm/amdgpu: remove DC special casing for KB/ML") |
| 41b497421a1f ("drm/amd/display: eDP sequence BL off first then DP blank.") |
| cf1835f03ffb ("drm/amd/display: fix backlight not off at resume from S4") |
| 31aec354f92c ("drm/amd/display: Implement interface for CRC on CRTC") |
| f8e413bf3c47 ("drm/amd/display: Move dpp reg access from hwss to dpp module.") |
| 405c50a07d3f ("drm/amd/display: Fix check for setting input TF") |
| c7e74f49598d ("drm/amd/display: Log which clocks are unsupported") |
| e07f541f50a3 ("drm/amd/display: Use real BE and FE index to program regs.") |
| c8242b9858ae ("drm/amd/display: Move hubp reg access from hwss to hubp module.") |
| 25292028d74b ("drm/amd/display: Disable eDP with a proper sequence.") |
| 91178796ba17 ("drm/amd/display: disable eDP backlight for extend monitor only reboot use case.") |
| 42e67c3b3c4a ("drm/amd/display: make FBC mem alloc dynamic") |
| 6d5d346f0462 ("drm/amd/display: Eliminate several Maximus-specific code paths") |
| a8c40b0b5add ("drm/amd/display: PME sw wa to support waking AZ D3") |
| e7899002cf20 ("drm/amd/display: Fix unused variable warnings.") |
| b51adc77e220 ("drm/amd/display: Only blank DCN when we have set_blank implementation") |
| 39f26499c6ff ("drm/amd/display: Put dcn_mi_registers with other structs") |
| 4b8240bf916f ("drm/amd/display: hubp refactor") |
| 36192e7e5703 ("drm/amd/display: Update HUBP") |
| 23bfb33181d2 ("drm/amd/display: Fix check for whether dmcu fw is running") |
