| 9c11b12184bb ("drm/i915/icl: Fix MG_DP_MODE() register programming") |
| 37fc7845df7b ("drm/i915: Call MG_DP_MODE() macro with the right parameters order") |
| 93b662d329d6 ("drm/i915/icl: Configure MG DP mode for HDMI ports too") |
| cb9ff519439b ("drm/i915/icl: Configure MG PHY gating for HDMI ports too") |
| de25eb7f3075 ("drm/i915: introduce dp_to_i915() helper") |
| bc334d914eee ("drm/i915/icl: toggle PHY clock gating around link training") |
| 340a44bef234 ("drm/i915/icl: program MG_DP_MODE") |
| afb2c4437dae ("drm/i915/ddi: Push pipe clock enabling to encoders") |
| 24a28179ecc0 ("drm/i915/ddi: s/crtc->config/old_crtc_state in haswell_crtc_disable()") |
| 59b74c497ae4 ("drm/i915: Clean up DP pipe select bits") |
| f67dc6d8869f ("drm/i915: Parametrize TRANS_DP_PORT_SEL") |
| b752e995829e ("drm/i915: Check for IVB instead of gen7 when we think about IVB CPU eDP") |
| 4718a365cf12 ("drm/i915: Use the same vswing->max_preemph mapping on HSW/BDW as on SKL+") |
| a393e9649582 ("drm/i915: Use intel_ddi_dp_voltage_max() for HSW/BDW too") |
| c8af5274c3cb ("drm/i915: enable the pipe/transcoder/planes later on HSW+") |
| 762034675ee7 ("drm/i915: Clean up SDVO pipe select bits") |
| a44628b9293b ("drm/i915: Clean up LVDS pipe select bits") |
| 6102a8ee8ad6 ("drm/i915: Clean up ADPA pipe select bits") |
| c27e917e2bda ("drm/i915/icl: add basic support for the ICL clocks") |
| fb5c8e9d4350 ("drm/i915/icl: Implement voltage swing programming sequence for Combo PHY DDI") |
| ef32659a78df ("drm/i915/dp: move eDP VBT bpp clamping code to intel_dp_compute_bpp()") |
| 981a63eb2725 ("drm/i915/dp: abstract dp link config computation from the rest") |
| dd519418f513 ("drm/i915/dp: move link_bw and rate_select debugging where used") |
| c92f47b5ec97 ("drm/i915/icl: Add register defs for voltage swing sequences for MG PHY DDI") |
| bba73071b6f7 ("Merge drm-next into drm-intel-next-queued (this time for real)") |
