| a5f2488f645f ("drm/i915: split intel_modeset_init() pre/post gem init") |
| 80f286a552c6 ("drm/i915: split intel_modeset_init() to pre/post irq install") |
| df1a5bfc16f3 ("drm/i915/psr: Force PSR probe only after full initialization") |
| b664259f3fe2 ("drm/i915: split i915_driver_modeset_probe() to pre/post irq install") |
| 93a0ed6cc164 ("drm/i915: split intel_modeset_driver_remove() to pre/post irq uninstall") |
| 8eecfb3985e8 ("drm/i915: switch i915_driver_probe() to use i915 local variable") |
| 46edcdbdb6d8 ("drm/i915: register vga switcheroo later, unregister earlier") |
| ceaaf5300f88 ("drm/i915/dc3co: Add description of how it works") |
| 1586f6200f69 ("drm/i915/display: Explicitly cleanup initial_plane_config") |
| 6471bd74713c ("drm/i915/psr: automatic conversion to drm_device based logging macros.") |
| 16c56083c0cb ("drm/i915/display/psr: Make WARN* drm specific where drm_priv ptr is available") |
| 0ef1905ecf2e ("drm/i915: Introduce better global state handling") |
| 5f34299384cb ("drm/i915: Move intel_atomic_state_free() into intel_atomic.c") |
| 1965de63a93a ("drm/i915: Extract intel_cdclk_state") |
| 5604e9ceaed5 ("drm/i915: Simplify intel_set_cdclk_{pre,post}_plane_update() calling convention") |
| 0bb94e03834e ("drm/i915: s/cdclk_state/cdclk_config/") |
| 65c88a866d70 ("drm/i915: s/need_cd2x_updare/can_cd2x_update/") |
| b4db3a8c689b ("drm/i915: Collect more cdclk state under the same roof") |
| 54f09d2342b0 ("drm/i915: Move more cdclk state handling into the cdclk code") |
| 6dcde04706d8 ("drm/i915: Move linetime wms into the crtc state") |
| 0560b0c6b36c ("drm/i915: Polish WM_LINETIME register stuff") |
| dc008bf0aa09 ("drm/i915/display: use intel_de_*() functions for register access") |
| c51e7138f66a ("drm/i915/psr: use intel_de_*() functions for register access") |
| 3e9f55df59f7 ("drm/i915/cdclk: use intel_de_*() functions for register access") |
| cd49f8180681 ("drm/i915/display: conversion to new struct drm_device logging macros.") |
| c5c772cf8d7c ("drm/i915/dc3co: Avoid full modeset when EXITLINE needs to be changed") |
| 58c34c4ca392 ("drm/i915/dc3co: Do the full calculation of DC3CO exit only once") |
| 231946109ea4 ("drm/i915/cdclk: use new struct drm_device logging macros") |
| 45e84648bb21 ("drm/i915/atomic: use struct drm_device logging macros") |
| 691313ea6214 ("drm/i915: Move encoder variable to tighter scope") |
| 9e83713a721b ("drm/i915/psr: Share the computation of idle frames") |
| 43a6d19cace6 ("drm/i915: Pass intel_connector to intel_attached_*()") |
| 60c6a14b489b ("drm/i915/display: Force the state compute phase once to enable PSR") |
| 2dfbf9d2873a ("drm/i915/tgl: Gen-12 display can decompress surfaces compressed by the media engine") |
| 5cf15dfca91c ("drm/i915: Add debug message for FB plane[0].offset!=0 error") |
| d156135e6a54 ("drm/i915/tgl: Make sure a semiplanar UV plane is tile row size aligned") |
| aee40639cdc3 ("drm/i915/dp: Make port sync mode assignments only if all tiles present") |
| 1e1a139d62d1 ("drm/i915: Extend WaDisableDARBFClkGating to icl,ehl,tgl") |
| 6671c367a9be ("drm/i915/tgl: Select master transcoder for MST stream") |
| ee36c7c0c837 ("drm/i915/display: Share intel_connector_needs_modeset()") |
| 4941f35b48f7 ("drm/i915: Make sure CCS YUV semiplanar format checks work") |
| 71df86f0fbf5 ("drm/i915/tgl: Make sure FBs have a correct CCS plane stride") |
| b3e57bccd68a ("drm/i915/tgl: Gen-12 render decompression") |
| e7af90945794 ("drm/i915: Add helpers to select correct ccs/aux planes") |
| 13f2cb9a2800 ("drm/i915: Extract framebufer CCS offset checks into a function") |
| 86f236bbbd88 ("drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment") |
| 979e94c1d64a ("drm/i915: Introduce intel_crtc_state_reset()") |
| 6643453987c4 ("drm/i915: Introduce intel_crtc_{alloc,free}()") |
| f44bfa7fbfbb ("drm/i915: s/intel_crtc/crtc/ in intel_crtc_init()") |
| b104e8b20097 ("drm/i915: Pass cpu transcoder to assert_pipe()") |
