| c2661638e886 ("drm/i915/icl: Power on DSI panel") |
| bfee32bfca82 ("drm/i915/icl: Set max return packet size for DSI panel") |
| d1aeb5f399d9 ("drm/i915/icl: Configure DSI transcoder timings") |
| 70f4f502c47e ("drm/i915/icl: Program TRANS_DDI_FUNC_CTL registers") |
| d364dc66e2d5 ("drm/i915/icl: Configure DSI transcoders") |
| ca8fc99f2ac1 ("drm/i915/icl: Get DSI transcoder for a given port") |
| 67551a703544 ("drm/i915/dsi: abstract dphy parameter init") |
| 2bf3f59daeee ("drm/i915/dsi: refactor bitrate calculations in intel_dsi_vbt_init()") |
| 70a7b83628fa ("drm/i915/icl: Program T_INIT_MASTER registers") |
| ba3df888be90 ("drm/i915/icl: Enable DDI Buffer") |
| 3f4b9d9d02c6 ("drm/i915/icl: DSI vswing programming sequence") |
| fc41001d9708 ("drm/i915/icl: Configure lane sequencing of combo phy transmitter") |
