| 34a3f0b273a7 ("drm/i915/display: Move out code to return the digital_port of the aux ch") |
| a66d7c1e8923 ("drm/i915/display/power: Make WARN* drm specific where drm_priv ptr is available") |
| b04002f4dbee ("drm/i915: Read rawclk_freq earlier") |
| 0f0f9aeee334 ("drm/i915: Manipulate DBuf slices properly") |
| 2570b7e3c561 ("drm/i915: Introduce parameterized DBUF_CTL") |
| b06cf5953339 ("drm/i915: Move dbuf slice update to proper place") |
| 072fcc306be3 ("drm/i915: Remove skl_ddl_allocation struct") |
| 0bb94e03834e ("drm/i915: s/cdclk_state/cdclk_config/") |
| 65c88a866d70 ("drm/i915: s/need_cd2x_updare/can_cd2x_update/") |
| b4db3a8c689b ("drm/i915: Collect more cdclk state under the same roof") |
| 54f09d2342b0 ("drm/i915: Move more cdclk state handling into the cdclk code") |
| f119a5e2a4ca ("drm/i915: Nuke skl wm.dirty_pipes bitmask") |
| 6dcde04706d8 ("drm/i915: Move linetime wms into the crtc state") |
| 0560b0c6b36c ("drm/i915: Polish WM_LINETIME register stuff") |
| d6e53851ecc8 ("drm/i915/display_power: use intel_de_*() functions for register access") |
| dc008bf0aa09 ("drm/i915/display: use intel_de_*() functions for register access") |
| 3e9f55df59f7 ("drm/i915/cdclk: use intel_de_*() functions for register access") |
| 569caa65a495 ("drm/i915/power: convert to struct drm_device macros in display/intel_display_power.c") |
| cd49f8180681 ("drm/i915/display: conversion to new struct drm_device logging macros.") |
| 231946109ea4 ("drm/i915/cdclk: use new struct drm_device logging macros") |
| 691313ea6214 ("drm/i915: Move encoder variable to tighter scope") |
| b7d02c3a124d ("drm/i915: Pass intel_encoder to enc_to_*()") |
| 43a6d19cace6 ("drm/i915: Pass intel_connector to intel_attached_*()") |
| 60c6a14b489b ("drm/i915/display: Force the state compute phase once to enable PSR") |
| 2dfbf9d2873a ("drm/i915/tgl: Gen-12 display can decompress surfaces compressed by the media engine") |
| 5cf15dfca91c ("drm/i915: Add debug message for FB plane[0].offset!=0 error") |
| d156135e6a54 ("drm/i915/tgl: Make sure a semiplanar UV plane is tile row size aligned") |
| aee40639cdc3 ("drm/i915/dp: Make port sync mode assignments only if all tiles present") |
| 1e1a139d62d1 ("drm/i915: Extend WaDisableDARBFClkGating to icl,ehl,tgl") |
| 659f14158f1f ("drm/i915/display: Always enables MST master pipe first") |
| 6671c367a9be ("drm/i915/tgl: Select master transcoder for MST stream") |
| ee36c7c0c837 ("drm/i915/display: Share intel_connector_needs_modeset()") |
| 4941f35b48f7 ("drm/i915: Make sure CCS YUV semiplanar format checks work") |
| 71df86f0fbf5 ("drm/i915/tgl: Make sure FBs have a correct CCS plane stride") |
| b3e57bccd68a ("drm/i915/tgl: Gen-12 render decompression") |
| e7af90945794 ("drm/i915: Add helpers to select correct ccs/aux planes") |
| 13f2cb9a2800 ("drm/i915: Extract framebufer CCS offset checks into a function") |
| 86f236bbbd88 ("drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment") |
| 17bef9baf339 ("drm/i915: Nuke .post_pll_disable() for DDI platforms") |
| 979e94c1d64a ("drm/i915: Introduce intel_crtc_state_reset()") |
| 6643453987c4 ("drm/i915: Introduce intel_crtc_{alloc,free}()") |
| f44bfa7fbfbb ("drm/i915: s/intel_crtc/crtc/ in intel_crtc_init()") |
| b69fa3610b15 ("drm/i915/icl: Cleanup combo PHY aux power well handlers") |
| 601a9ee0f0c7 ("drm/i915: Streamline skl_commit_modeset_enables()") |
| b104e8b20097 ("drm/i915: Pass cpu transcoder to assert_pipe()") |
| a722146b5f52 ("drm/i915: ELiminate intel_pipe_to_cpu_transcoder() from assert_fdi_tx()") |
| 2b68392e638d ("drm/i915/dsi: add support for DSC") |
| 0486513935ef ("drm/i915/dsi: take compression into account in afe_clk()") |
| adf1bd3dfbae ("drm/i915/dsi: use afe_clk() instead of intel_dsi_bitrate()") |
| 54ed6902cabc ("drm/i915/dsi: abstract afe_clk calculation") |
