| 20f505f22531 ("drm/i915: Restrict qgv points which don't have enough bandwidth.") |
| d8d5afe35e3f ("drm/i915: Make active_pipes check skl specific") |
| 1d0a6c8486aa ("drm/i915: Extract skl SAGV checking") |
| 9ff79708c54d ("drm/i915: Rename bw_state to new_bw_state") |
| ecab0f3d055d ("drm/i915: Track active_pipes in bw_state") |
| 9728889f42b9 ("drm/i915: Use bw state for per crtc SAGV evaluation") |
| 680e1af713d9 ("drm/i915: Add pre/post plane updates for SAGV") |
| a389c49fac55 ("drm/i915: Prepare to extract gen specific functions from intel_can_enable_sagv") |
| 23baedd217ef ("drm/i915: Don't check for wm changes until we've compute the wms fully") |
| ff2cd8635e41 ("drm/i915: Correctly map DBUF slices to pipes") |
| 0f0f9aeee334 ("drm/i915: Manipulate DBuf slices properly") |
| 2570b7e3c561 ("drm/i915: Introduce parameterized DBUF_CTL") |
| b06cf5953339 ("drm/i915: Move dbuf slice update to proper place") |
| 072fcc306be3 ("drm/i915: Remove skl_ddl_allocation struct") |
| fd1a9bba73fa ("drm/i915: Convert bandwidth state to global state") |
| f119a5e2a4ca ("drm/i915: Nuke skl wm.dirty_pipes bitmask") |
| 6dcde04706d8 ("drm/i915: Move linetime wms into the crtc state") |
| 0560b0c6b36c ("drm/i915: Polish WM_LINETIME register stuff") |
| d6e53851ecc8 ("drm/i915/display_power: use intel_de_*() functions for register access") |
| dc008bf0aa09 ("drm/i915/display: use intel_de_*() functions for register access") |
| 569caa65a495 ("drm/i915/power: convert to struct drm_device macros in display/intel_display_power.c") |
| cd49f8180681 ("drm/i915/display: conversion to new struct drm_device logging macros.") |
| 2e3586cec3eb ("drm/i915/bw: convert to drm_device based logging macros") |
| 691313ea6214 ("drm/i915: Move encoder variable to tighter scope") |
| 43a6d19cace6 ("drm/i915: Pass intel_connector to intel_attached_*()") |
| 2dfbf9d2873a ("drm/i915/tgl: Gen-12 display can decompress surfaces compressed by the media engine") |
| 5cf15dfca91c ("drm/i915: Add debug message for FB plane[0].offset!=0 error") |
| d156135e6a54 ("drm/i915/tgl: Make sure a semiplanar UV plane is tile row size aligned") |
| aee40639cdc3 ("drm/i915/dp: Make port sync mode assignments only if all tiles present") |
| 1e1a139d62d1 ("drm/i915: Extend WaDisableDARBFClkGating to icl,ehl,tgl") |
| 659f14158f1f ("drm/i915/display: Always enables MST master pipe first") |
| 6671c367a9be ("drm/i915/tgl: Select master transcoder for MST stream") |
| ee36c7c0c837 ("drm/i915/display: Share intel_connector_needs_modeset()") |
| 4941f35b48f7 ("drm/i915: Make sure CCS YUV semiplanar format checks work") |
| 71df86f0fbf5 ("drm/i915/tgl: Make sure FBs have a correct CCS plane stride") |
| b3e57bccd68a ("drm/i915/tgl: Gen-12 render decompression") |
| e7af90945794 ("drm/i915: Add helpers to select correct ccs/aux planes") |
| 13f2cb9a2800 ("drm/i915: Extract framebufer CCS offset checks into a function") |
| 86f236bbbd88 ("drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment") |
| 979e94c1d64a ("drm/i915: Introduce intel_crtc_state_reset()") |
| 6643453987c4 ("drm/i915: Introduce intel_crtc_{alloc,free}()") |
| f44bfa7fbfbb ("drm/i915: s/intel_crtc/crtc/ in intel_crtc_init()") |
| b69fa3610b15 ("drm/i915/icl: Cleanup combo PHY aux power well handlers") |
| 601a9ee0f0c7 ("drm/i915: Streamline skl_commit_modeset_enables()") |
| b104e8b20097 ("drm/i915: Pass cpu transcoder to assert_pipe()") |
| a722146b5f52 ("drm/i915: ELiminate intel_pipe_to_cpu_transcoder() from assert_fdi_tx()") |
| fbacb15ea814 ("drm/i915/dsc: add basic hardware state readout support") |
| 2d15f3925a4b ("drm/i915/dsc: add support for computing and writing PPS for DSI encoders") |
| 3fa01d642fa7 ("drm/i915/tgl: Program BW_BUDDY registers during display init") |
| 04da7b9f9af6 ("drm/i915: Relocate intel_crtc_active()") |
