| cd803bb4f8a8 ("drm/i915/rkl: Handle new DPCLKA_CFGCR0 layout") |
| dc008bf0aa09 ("drm/i915/display: use intel_de_*() functions for register access") |
| f7960e7f8f24 ("drm/i915/ddi: use intel_de_*() functions for register access") |
| cd49f8180681 ("drm/i915/display: conversion to new struct drm_device logging macros.") |
| 691313ea6214 ("drm/i915: Move encoder variable to tighter scope") |
| b7d02c3a124d ("drm/i915: Pass intel_encoder to enc_to_*()") |
| 43a6d19cace6 ("drm/i915: Pass intel_connector to intel_attached_*()") |
| 60c6a14b489b ("drm/i915/display: Force the state compute phase once to enable PSR") |
| 2dfbf9d2873a ("drm/i915/tgl: Gen-12 display can decompress surfaces compressed by the media engine") |
| 5cf15dfca91c ("drm/i915: Add debug message for FB plane[0].offset!=0 error") |
| d156135e6a54 ("drm/i915/tgl: Make sure a semiplanar UV plane is tile row size aligned") |
| a3d9382bd439 ("drm/i915/dp: Disable Port sync mode correctly on teardown") |
| aee40639cdc3 ("drm/i915/dp: Make port sync mode assignments only if all tiles present") |
| 1e1a139d62d1 ("drm/i915: Extend WaDisableDARBFClkGating to icl,ehl,tgl") |
| c59053dc58fa ("drm/i915/dp: Fix MST disable sequence") |
| 6671c367a9be ("drm/i915/tgl: Select master transcoder for MST stream") |
| ee36c7c0c837 ("drm/i915/display: Share intel_connector_needs_modeset()") |
| 4941f35b48f7 ("drm/i915: Make sure CCS YUV semiplanar format checks work") |
| 71df86f0fbf5 ("drm/i915/tgl: Make sure FBs have a correct CCS plane stride") |
| b3e57bccd68a ("drm/i915/tgl: Gen-12 render decompression") |
| e7af90945794 ("drm/i915: Add helpers to select correct ccs/aux planes") |
| 13f2cb9a2800 ("drm/i915: Extract framebufer CCS offset checks into a function") |
| 86f236bbbd88 ("drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment") |
| 5956f44028f5 ("drm/i915/display: move clk off sanitize to its own function") |
| 773b4b54351c ("drm/i915: Move stuff from haswell_crtc_disable() into encoder .post_disable()") |
| f5271ee50d28 ("drm/i915: Pass old crtc state to intel_crtc_vblank_off()") |
| cfb627c44851 ("drm/i915: Pass old crtc state to skylake_scaler_disable()") |
| 17bef9baf339 ("drm/i915: Nuke .post_pll_disable() for DDI platforms") |
| 979e94c1d64a ("drm/i915: Introduce intel_crtc_state_reset()") |
| 6643453987c4 ("drm/i915: Introduce intel_crtc_{alloc,free}()") |
| f44bfa7fbfbb ("drm/i915: s/intel_crtc/crtc/ in intel_crtc_init()") |
| b104e8b20097 ("drm/i915: Pass cpu transcoder to assert_pipe()") |
| a722146b5f52 ("drm/i915: ELiminate intel_pipe_to_cpu_transcoder() from assert_fdi_tx()") |
| 2b68392e638d ("drm/i915/dsi: add support for DSC") |
| 0486513935ef ("drm/i915/dsi: take compression into account in afe_clk()") |
| adf1bd3dfbae ("drm/i915/dsi: use afe_clk() instead of intel_dsi_bitrate()") |
| 54ed6902cabc ("drm/i915/dsi: abstract afe_clk calculation") |
| fbacb15ea814 ("drm/i915/dsc: add basic hardware state readout support") |
| 2d15f3925a4b ("drm/i915/dsc: add support for computing and writing PPS for DSI encoders") |
| 7a7b5be96fb6 ("drm/i915/dsc: move DP specific compute params to intel_dp.c") |
| 04da7b9f9af6 ("drm/i915: Relocate intel_crtc_active()") |
| ad457191015a ("drm/i915/display: Refactor intel_commit_modeset_disables()") |
| 3ca8f1918883 ("drm/i915/display/tgl: Fix the order of the step to turn transcoder clock off") |
| bee43ca4c1cc ("drm/i915: Clean up intel_{pre,post}_plane_update()") |
| 0e75fb8c03aa ("drm/i915: s/pipe_config/new_crtc_state/ intel_{pre,post}_plane_update()") |
| 60aca5741a69 ("drm/i915: Pass dev_priv to ilk_disable_lp_wm()") |
| d2432796dc72 ("drm/i915: Clean up arguments to nv12/scaler w/a funcs") |
| 78eaaba3cd78 ("drm/i915/display/mst: Move DPMS_OFF call to post_disable") |
| 50a7efb280a8 ("drm/i915/dp: Power down sink before disable pipe/transcoder clock") |
| e815aff59dcf ("drm/i915/display: Check the old state to find port sync slave") |
