| 70a7b83628fa ("drm/i915/icl: Program T_INIT_MASTER registers") |
| ba3df888be90 ("drm/i915/icl: Enable DDI Buffer") |
| 3f4b9d9d02c6 ("drm/i915/icl: DSI vswing programming sequence") |
| fc41001d9708 ("drm/i915/icl: Configure lane sequencing of combo phy transmitter") |
| 45f09f7adc8a ("drm/i915/icl: Power down unused DSI lanes") |
| b1cb21a5f1c6 ("drm/i915/icl: Enable DSI IO power") |
| fcfe0bdcb191 ("drm/i915/icl: Program DSI Escape clock Divider") |
| 27efd2566cb8 ("drm/i915/icl: Define register for DSI PLL") |
| aec0246f3e38 ("drm/i915: Enable scanline read based on frame timestamps") |
