| d95f1a542c3d ("RISC-V: Implement sparsemem") |
| 671f9a3e2e24 ("RISC-V: Setup initial page tables in two stages") |
| 9e953cda5cdf ("riscv: Introduce huge page support for 32/64bit kernel") |
| d90d45d7dcb7 ("RISC-V: Fix memory reservation in setup_bootmem()") |
| 50acfb2b76e1 ("treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286") |
| a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs") |
| f6635f873a60 ("riscv: move switch_mm to its own file") |
| a3182c91ef4e ("RISC-V: Access CSRs using CSR numbers") |
| ba9c0141941c ("riscv: cleanup the parse_dtb calling conventions") |
| df16c40cbfb4 ("riscv: clear all pending interrupts when booting") |
| 387181dcdb6c ("RISC-V: Always compile mm/init.c with cmodel=medany and notrace") |
| d72cb8c7d9db ("Merge tag 'riscv-for-linus-5.1-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux") |
