| 56ed441aa1ed ("drm/i915/ehl: Check PHY type before reading DPLL frequency") |
| 45e4728b87ad ("drm/i915: Move DPLL frequency calculation to intel_dpll_mgr.c") |
| 6cbcd57680e1 ("drm/i915/hsw: Use the DPLL ID when calculating DPLL clock") |
| 830b2cdcf4cc ("drm/i915: Move DPLL HW readout/sanitize fns to intel_dpll_mgr.c") |
| 1de143cc5b60 ("drm/i915/display/ddi: Make WARN* drm specific where drm_device ptr is available") |
| 0c2d55128f33 ("drm/i915: Store active_pipes bitmask in cdclk state") |
| 28a30b45f5e9 ("drm/i915: Convert cdclk to global state") |
| 0ef1905ecf2e ("drm/i915: Introduce better global state handling") |
| 5f34299384cb ("drm/i915: Move intel_atomic_state_free() into intel_atomic.c") |
| 4c029c499fb4 ("drm/i915: swap() the entire cdclk state") |
| 1965de63a93a ("drm/i915: Extract intel_cdclk_state") |
| 5604e9ceaed5 ("drm/i915: Simplify intel_set_cdclk_{pre,post}_plane_update() calling convention") |
| 0bb94e03834e ("drm/i915: s/cdclk_state/cdclk_config/") |
| 65c88a866d70 ("drm/i915: s/need_cd2x_updare/can_cd2x_update/") |
| b4db3a8c689b ("drm/i915: Collect more cdclk state under the same roof") |
| 54f09d2342b0 ("drm/i915: Move more cdclk state handling into the cdclk code") |
| 6dcde04706d8 ("drm/i915: Move linetime wms into the crtc state") |
| 0560b0c6b36c ("drm/i915: Polish WM_LINETIME register stuff") |
| dc008bf0aa09 ("drm/i915/display: use intel_de_*() functions for register access") |
| f7960e7f8f24 ("drm/i915/ddi: use intel_de_*() functions for register access") |
| 3e9f55df59f7 ("drm/i915/cdclk: use intel_de_*() functions for register access") |
| cd49f8180681 ("drm/i915/display: conversion to new struct drm_device logging macros.") |
| 231946109ea4 ("drm/i915/cdclk: use new struct drm_device logging macros") |
| 45e84648bb21 ("drm/i915/atomic: use struct drm_device logging macros") |
| 3a47ae201e07 ("drm/i915/display: Make WARN* drm specific where encoder ptr is available") |
| 691313ea6214 ("drm/i915: Move encoder variable to tighter scope") |
| b7d02c3a124d ("drm/i915: Pass intel_encoder to enc_to_*()") |
| 43a6d19cace6 ("drm/i915: Pass intel_connector to intel_attached_*()") |
| 542dfab53ed0 ("drm/i915/display: Fix warning about MST and DDI restrictions") |
| 60c6a14b489b ("drm/i915/display: Force the state compute phase once to enable PSR") |
| 2dfbf9d2873a ("drm/i915/tgl: Gen-12 display can decompress surfaces compressed by the media engine") |
| 5cf15dfca91c ("drm/i915: Add debug message for FB plane[0].offset!=0 error") |
| d156135e6a54 ("drm/i915/tgl: Make sure a semiplanar UV plane is tile row size aligned") |
| a3d9382bd439 ("drm/i915/dp: Disable Port sync mode correctly on teardown") |
| aee40639cdc3 ("drm/i915/dp: Make port sync mode assignments only if all tiles present") |
| 1e1a139d62d1 ("drm/i915: Extend WaDisableDARBFClkGating to icl,ehl,tgl") |
| c59053dc58fa ("drm/i915/dp: Fix MST disable sequence") |
| 6671c367a9be ("drm/i915/tgl: Select master transcoder for MST stream") |
| ee36c7c0c837 ("drm/i915/display: Share intel_connector_needs_modeset()") |
| 4941f35b48f7 ("drm/i915: Make sure CCS YUV semiplanar format checks work") |
| 71df86f0fbf5 ("drm/i915/tgl: Make sure FBs have a correct CCS plane stride") |
| b3e57bccd68a ("drm/i915/tgl: Gen-12 render decompression") |
| e7af90945794 ("drm/i915: Add helpers to select correct ccs/aux planes") |
| 13f2cb9a2800 ("drm/i915: Extract framebufer CCS offset checks into a function") |
| 86f236bbbd88 ("drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment") |
| 5956f44028f5 ("drm/i915/display: move clk off sanitize to its own function") |
| 773b4b54351c ("drm/i915: Move stuff from haswell_crtc_disable() into encoder .post_disable()") |
| f5271ee50d28 ("drm/i915: Pass old crtc state to intel_crtc_vblank_off()") |
| cfb627c44851 ("drm/i915: Pass old crtc state to skylake_scaler_disable()") |
| 17bef9baf339 ("drm/i915: Nuke .post_pll_disable() for DDI platforms") |
