| 6b5d7730d226 ("drm/amd/display: Add wait for flip not pending on pipe unlock") |
| f2988e67144a ("drm/amd/display: optimize bandwidth after commit streams.") |
| 1ea8751bd28d ("drm/amd/display: Make clk mgr the only dto update point") |
| 799c5b9cb91c ("drm/amd/display: Revert fixup DPP programming sequence") |
| a45804db8bc0 ("drm/amd/display: Replace for loop w/ function call") |
| b6e881c94741 ("drm/amd/display: update navi to use new surface programming behaviour") |
| 4edb6fc91878 ("drm/amd/display: Add Renoir clock manager") |
| 285e30049708 ("drm/amd/display: fix dcn20 odm dpp programming") |
| b1f6d01c4a3b ("drm/amd/display: re structure odm to allow 4 to 1 support") |
| 4c3cfe14c04e ("Revert "drm/amd/display: add global master update lock for DCN2"") |
| 544618596fd5 ("drm/amd/display: wake up ogam mem pwr before programming ocsc") |
| 2b162fd30249 ("drm/amd/display: update optc odm interface for more than 2 opps") |
| c681491a0921 ("drm/amd/display: fix pipe selection logic in validate") |
| 1a9e3d4569fc ("drm/amd/display: Set DSC before DIG front-end is connected to its back-end") |
| 8a31820b1218 ("drm/amd/display: Make init_hw and init_pipes generic for seamless boot") |
| 986936d1a9b2 ("drm/amd/display: wait for pending complete when enabling a plane") |
| f7f38ffef56b ("drm/amd/display: fixup DPP programming sequence") |
| 9adc8050bf3c ("drm/amd/display: make firmware info only load once during dc_bios create") |
| d3b9f39d8417 ("drm/amdgpu/display: fix the build without CONFIG_DRM_AMD_DC_DSC_SUPPORT") |
| 21ffcc94d5b3 ("drm/amd/display: Copy GSL groups when committing a new context") |
| 057fc695e934 ("drm/amd/display: support "dummy pstate"") |
| f591344e89dc ("drm/amd/display: Clean up dynamic metadata logic") |
| 39bca3599aab ("drm/amd/display: add a option to force the clock at every mode change.") |
| 925f566cb7ae ("drm/amd/display: add set and get clock for testing purposes") |
| 290129c25617 ("drm/amd/display: Add CM_BYPASS via debug option") |
| 70f1476a7eed ("drm/amd/display: Add debug option to disable timing sync") |
| c43f89f81cc0 ("drm/amd/display: put back front end initialization sequence") |
| 75c35000235f ("drm/amd/display: Power-gate all DSCs at driver init time") |
| 24f1d1cee2bc ("drm/amd/display: Check for valid stream_encode") |
| 606b355170b5 ("drm/amd/display: add hdmi2.1 dsc pps packet programming") |
| 6de202373bf6 ("drm/amd/display: move bw calc code into helpers") |
| ec16ac6b4264 ("drm/amd/display: fix dsc disable") |
| 93c25fbdc30a ("drm/amd/display: initialize p_state to proper value") |
| 41a5a2a8531f ("drm/amd/display: init res_pool dccg_ref, dchub_ref with xtalin_freq") |
| 709527c77a89 ("drm/amd/display: update infoframe after dig fe is turned on (v2)") |
| ed9656fbc8b5 ("drm/amd/amdgpu: Check stream in amdgpu_dm_commit_planes") |
| 170a2398d2d8 ("drm/amd/display: make clk_mgr call enable_pme_wa") |
| 7a5ab155d34a ("drm/amd/display: expose dentist_get_did_from_divider") |
| 1a7d296d162e ("drm/amd/display: Add Underflow Asserts to dc") |
| a6465d1f3b8f ("drm/amd/display: dcn2 use fixed clocks.") |
| 6e17b5b8a846 ("drm/amd/display: update DCN2 uclk switch time") |
| 043f5bb630c1 ("drm/amd/display: Use macro for invalid OPP ID") |
| f82c916c4197 ("drm/amd/display: add some parameters to validate bandwidth functions") |
| 2131f65581ba ("drm/amd/display: add support for forcing DCFCLK without affecting watermarks") |
| a746a2585542 ("drm/amd/display: Drive-by fixes for display_mode_vba") |
| 98ce8cc1b47a ("drm/amd/display: Enable DSC power-gating for DSC streams") |
| c3ec8ba53779 ("drm/amd/display: Return UPDATE_TYPE_FULL on writeback update") |
| ba32c50f0446 ("drm/amd/display: decouple dsc adjustment out of enablement") |
| 278141f58e2c ("drm/amd/display: Use DCN2 functions instead of DCE") |
| 6936c8b1d415 ("drm/amd/display: DCN2 Engine-specifc encoder allocation") |
