| 7d4b5ca2e2cb ("cxl/acpi: Add downstream port data to cxl_port instances") |
| 4812be97c015 ("cxl/acpi: Introduce the root of a cxl_port topology") |
| 08422378c4ad ("cxl/pci: Add HDM decoder capabilities") |
| 9a016527dcb7 ("cxl/pci: Reserve individual register block regions") |
| 30af97296f48 ("cxl/pci: Map registers based on capabilities") |
| f8a7e8c29be8 ("cxl/pci: Reserve all device regions at once") |
| 07d62eac422c ("cxl/pci: Introduce cxl_decode_register_block()") |
| 6630d31c912e ("cxl/mem: Get rid of @cxlm.base") |
| 1d5a4159074b ("cxl/mem: Move register locator logic into reg setup") |
| 1b0a1a2a1934 ("cxl/mem: Split creation from mapping in probe") |
| 21e9f76733a8 ("cxl: Rename mem to pci") |
| 35c32e3095d3 ("cxl/docs: Fix "Title underline too short" warning") |
| 399d34ebc248 ("cxl/core: Refactor CXL register lookup for bridge reuse") |
| 5f653f7590ab ("cxl/core: Rename bus.c to core.c") |
| 8ac75dd6ab30 ("cxl/mem: Introduce 'struct cxl_regs' for "composable" CXL devices") |
| 5f50d6b20ca3 ("cxl/mem: Move some definitions to mem.h") |
| b21bb4cd1102 ("cxl/mem: Fix register block offset calculation") |
| 5877515912cc ("cxl/mem: Fix synchronization mechanism for device removal vs ioctl operations") |
| 472b1ce6e9d6 ("cxl/mem: Enable commands via CEL") |
| 13237183c735 ("cxl/mem: Add a "RAW" send command") |
