| e5f7e81ee430 ("mmc: renesas_sdhi: Parse DT for SDnH") |
| bb6d3fa98a41 ("clk: renesas: rcar-gen3: Switch to new SD clock handling") |
| a31cf51bf6b4 ("clk: renesas: rcar-gen3: Add dummy SDnH clock") |
| f2fb4fe62390 ("clk: renesas: Zero init clk_init_data") |
| 792501727c2a ("clk: renesas: r8a779a0: Add SDHI support") |
| 8bb67d87346a ("clk: renesas: rcar-gen3: Factor out CPG library") |
| 97af391a6fdc ("clk: renesas: rcar-gen3: Remove cpg_quirks access when registering SD clock") |
| 14653942de7f ("clk: renesas: r8a779a0: Fix R and OSC clocks") |
| 874d4eee5421 ("clk: renesas: r8a779a0: Add VIN clocks") |
| 7f2c2f38c1c0 ("clk: renesas: rcar-gen3: Remove stp_ck handling for SDHI") |
| 15d683e61bdd ("clk: renesas: rcar-gen3: Update description for RZ/G2") |
| 17bcc8035d2d ("clk: renesas: cpg-mssr: Add support for R-Car V3U") |
| 8b652aa8a1fb ("clk: renesas: cpg-mssr: Add register pointers into struct cpg_mssr_priv") |
| ffbf9cf3f946 ("clk: renesas: cpg-mssr: Use enum clk_reg_layout instead of a boolean flag") |
