| /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ |
| /* |
| * Author: Yinbo Zhu <zhuyinbo@loongson.cn> |
| * Copyright (C) 2022-2023 Loongson Technology Corporation Limited |
| */ |
| |
| #ifndef __DT_BINDINGS_CLOCK_LOONGSON2_H |
| #define __DT_BINDINGS_CLOCK_LOONGSON2_H |
| |
| #define LOONGSON2_REF_100M 0 |
| #define LOONGSON2_NODE_PLL 1 |
| #define LOONGSON2_DDR_PLL 2 |
| #define LOONGSON2_DC_PLL 3 |
| #define LOONGSON2_PIX0_PLL 4 |
| #define LOONGSON2_PIX1_PLL 5 |
| #define LOONGSON2_NODE_CLK 6 |
| #define LOONGSON2_HDA_CLK 7 |
| #define LOONGSON2_GPU_CLK 8 |
| #define LOONGSON2_DDR_CLK 9 |
| #define LOONGSON2_GMAC_CLK 10 |
| #define LOONGSON2_DC_CLK 11 |
| #define LOONGSON2_APB_CLK 12 |
| #define LOONGSON2_USB_CLK 13 |
| #define LOONGSON2_SATA_CLK 14 |
| #define LOONGSON2_PIX0_CLK 15 |
| #define LOONGSON2_PIX1_CLK 16 |
| #define LOONGSON2_BOOT_CLK 17 |
| #define LOONGSON2_OUT0_GATE 18 |
| #define LOONGSON2_GMAC_GATE 19 |
| #define LOONGSON2_RIO_GATE 20 |
| #define LOONGSON2_DC_GATE 21 |
| #define LOONGSON2_GPU_GATE 22 |
| #define LOONGSON2_DDR_GATE 23 |
| #define LOONGSON2_HDA_GATE 24 |
| #define LOONGSON2_NODE_GATE 25 |
| #define LOONGSON2_EMMC_GATE 26 |
| #define LOONGSON2_PIX0_GATE 27 |
| #define LOONGSON2_PIX1_GATE 28 |
| #define LOONGSON2_OUT0_CLK 29 |
| #define LOONGSON2_RIO_CLK 30 |
| #define LOONGSON2_EMMC_CLK 31 |
| #define LOONGSON2_DES_CLK 32 |
| #define LOONGSON2_I2S_CLK 33 |
| #define LOONGSON2_MISC_CLK 34 |
| |
| #define LS2K0300_CLK_STABLE 0 |
| #define LS2K0300_NODE_PLL 1 |
| #define LS2K0300_DDR_PLL 2 |
| #define LS2K0300_PIX_PLL 3 |
| #define LS2K0300_CLK_THSENS 4 |
| #define LS2K0300_CLK_NODE_DIV 5 |
| #define LS2K0300_CLK_NODE_PLL_GATE 6 |
| #define LS2K0300_CLK_NODE_SCALE 7 |
| #define LS2K0300_CLK_NODE_GATE 8 |
| #define LS2K0300_CLK_GMAC_DIV 9 |
| #define LS2K0300_CLK_GMAC_GATE 10 |
| #define LS2K0300_CLK_I2S_DIV 11 |
| #define LS2K0300_CLK_I2S_SCALE 12 |
| #define LS2K0300_CLK_I2S_GATE 13 |
| #define LS2K0300_CLK_DDR_DIV 14 |
| #define LS2K0300_CLK_DDR_GATE 15 |
| #define LS2K0300_CLK_NET_DIV 16 |
| #define LS2K0300_CLK_NET_GATE 17 |
| #define LS2K0300_CLK_DEV_DIV 18 |
| #define LS2K0300_CLK_DEV_GATE 19 |
| #define LS2K0300_CLK_PIX_DIV 20 |
| #define LS2K0300_CLK_PIX_PLL_GATE 21 |
| #define LS2K0300_CLK_PIX_SCALE 22 |
| #define LS2K0300_CLK_PIX_GATE 23 |
| #define LS2K0300_CLK_GMACBP_DIV 24 |
| #define LS2K0300_CLK_GMACBP_GATE 25 |
| #define LS2K0300_CLK_USB_SCALE 26 |
| #define LS2K0300_CLK_USB_GATE 27 |
| #define LS2K0300_CLK_APB_SCALE 28 |
| #define LS2K0300_CLK_APB_GATE 29 |
| #define LS2K0300_CLK_BOOT_SCALE 30 |
| #define LS2K0300_CLK_BOOT_GATE 31 |
| #define LS2K0300_CLK_SDIO_SCALE 32 |
| #define LS2K0300_CLK_SDIO_GATE 33 |
| #define LS2K0300_CLK_GMAC_IN 34 |
| |
| #endif |
