| /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ |
| /* |
| * Copyright 2025 Linaro Ltd. |
| * |
| * Device Tree binding constants for Google gs101 ACPM clock controller. |
| */ |
| |
| #ifndef _DT_BINDINGS_CLOCK_GOOGLE_GS101_ACPM_H |
| #define _DT_BINDINGS_CLOCK_GOOGLE_GS101_ACPM_H |
| |
| #define GS101_CLK_ACPM_DVFS_MIF 0 |
| #define GS101_CLK_ACPM_DVFS_INT 1 |
| #define GS101_CLK_ACPM_DVFS_CPUCL0 2 |
| #define GS101_CLK_ACPM_DVFS_CPUCL1 3 |
| #define GS101_CLK_ACPM_DVFS_CPUCL2 4 |
| #define GS101_CLK_ACPM_DVFS_G3D 5 |
| #define GS101_CLK_ACPM_DVFS_G3DL2 6 |
| #define GS101_CLK_ACPM_DVFS_TPU 7 |
| #define GS101_CLK_ACPM_DVFS_INTCAM 8 |
| #define GS101_CLK_ACPM_DVFS_TNR 9 |
| #define GS101_CLK_ACPM_DVFS_CAM 10 |
| #define GS101_CLK_ACPM_DVFS_MFC 11 |
| #define GS101_CLK_ACPM_DVFS_DISP 12 |
| #define GS101_CLK_ACPM_DVFS_BO 13 |
| |
| #endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_ACPM_H */ |
