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kernel/pub/scm/linux/kernel/git/stable/linux-stable/master/./drivers/clk/qcom/gcc-eliza.c
blob: 24c3aae0810f326671d2dd756be59abea250e27a [file]
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,eliza-gcc.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
#include "clk-regmap-phy-mux.h"
#include "common.h"
#include "gdsc.h"
#include "reset.h"
enum {
DT_BI_TCXO,
DT_SLEEP_CLK,
DT_PCIE_0_PIPE_CLK,
DT_PCIE_1_PIPE_CLK,
DT_UFS_PHY_RX_SYMBOL_0_CLK,
DT_UFS_PHY_RX_SYMBOL_1_CLK,
DT_UFS_PHY_TX_SYMBOL_0_CLK,
DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,
};
enum {
P_BI_TCXO,
P_GCC_GPLL0_OUT_EVEN,
P_GCC_GPLL0_OUT_MAIN,
P_GCC_GPLL4_OUT_MAIN,
P_GCC_GPLL7_OUT_MAIN,
P_GCC_GPLL8_OUT_MAIN,
P_GCC_GPLL9_OUT_MAIN,
P_PCIE_0_PIPE_CLK,
P_PCIE_1_PIPE_CLK,
P_SLEEP_CLK,
P_UFS_PHY_RX_SYMBOL_0_CLK,
P_UFS_PHY_RX_SYMBOL_1_CLK,
P_UFS_PHY_TX_SYMBOL_0_CLK,
P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,
};
static struct clk_alpha_pll gcc_gpll0 = {
.offset = 0x0,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr = {
.enable_reg = 0x52020,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gpll0",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
},
},
};
static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = {
{ 0x1, 2 },
{ }
};
static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
.offset = 0x0,
.post_div_shift = 10,
.post_div_table = post_div_table_gcc_gpll0_out_even,
.num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
.width = 4,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_gpll0_out_even",
.parent_hws = (const struct clk_hw*[]) {
&gcc_gpll0.clkr.hw,
},
.num_parents = 1,
.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
},
};
static struct clk_alpha_pll gcc_gpll4 = {
.offset = 0x4000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr = {
.enable_reg = 0x52020,
.enable_mask = BIT(4),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gpll4",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
},
},
};
static struct clk_alpha_pll gcc_gpll7 = {
.offset = 0x7000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr = {
.enable_reg = 0x52020,
.enable_mask = BIT(7),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gpll7",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
},
},
};
static struct clk_alpha_pll gcc_gpll8 = {
.offset = 0x8000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr = {
.enable_reg = 0x52020,
.enable_mask = BIT(8),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gpll8",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
},
},
};
static struct clk_alpha_pll gcc_gpll9 = {
.offset = 0x9000,
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
.clkr = {
.enable_reg = 0x52020,
.enable_mask = BIT(9),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gpll9",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
},
},
};
static const struct parent_map gcc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
{ P_GCC_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_0[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gcc_gpll0.clkr.hw },
{ .hw = &gcc_gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_1[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
{ P_SLEEP_CLK, 5 },
{ P_GCC_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_1[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gcc_gpll0.clkr.hw },
{ .index = DT_SLEEP_CLK },
{ .hw = &gcc_gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_2[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
{ P_GCC_GPLL4_OUT_MAIN, 5 },
{ P_GCC_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_2[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gcc_gpll0.clkr.hw },
{ .hw = &gcc_gpll4.clkr.hw },
{ .hw = &gcc_gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_3[] = {
{ P_BI_TCXO, 0 },
{ P_SLEEP_CLK, 5 },
};
static const struct clk_parent_data gcc_parent_data_3[] = {
{ .index = DT_BI_TCXO },
{ .index = DT_SLEEP_CLK },
};
static const struct parent_map gcc_parent_map_4[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
{ P_GCC_GPLL7_OUT_MAIN, 2 },
{ P_GCC_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_4[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gcc_gpll0.clkr.hw },
{ .hw = &gcc_gpll7.clkr.hw },
{ .hw = &gcc_gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_5[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
{ P_GCC_GPLL8_OUT_MAIN, 2 },
{ P_GCC_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_5[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gcc_gpll0.clkr.hw },
{ .hw = &gcc_gpll8.clkr.hw },
{ .hw = &gcc_gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_6[] = {
{ P_BI_TCXO, 0 },
};
static const struct clk_parent_data gcc_parent_data_6[] = {
{ .index = DT_BI_TCXO },
};
static const struct parent_map gcc_parent_map_7[] = {
{ P_BI_TCXO, 0 },
{ P_GCC_GPLL0_OUT_MAIN, 1 },
{ P_GCC_GPLL9_OUT_MAIN, 2 },
{ P_GCC_GPLL4_OUT_MAIN, 5 },
{ P_GCC_GPLL0_OUT_EVEN, 6 },
};
static const struct clk_parent_data gcc_parent_data_7[] = {
{ .index = DT_BI_TCXO },
{ .hw = &gcc_gpll0.clkr.hw },
{ .hw = &gcc_gpll9.clkr.hw },
{ .hw = &gcc_gpll4.clkr.hw },
{ .hw = &gcc_gpll0_out_even.clkr.hw },
};
static const struct parent_map gcc_parent_map_8[] = {
{ P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
{ P_BI_TCXO, 2 },
{ P_GCC_GPLL0_OUT_EVEN, 3 },
};
static const struct clk_parent_data gcc_parent_data_8[] = {
{ .index = DT_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK },
{ .index = DT_BI_TCXO },
{ .hw = &gcc_gpll0_out_even.clkr.hw },
};
static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = {
.reg = 0x6b080,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_0_pipe_clk_src",
.parent_data = &(const struct clk_parent_data){
.index = DT_PCIE_0_PIPE_CLK,
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
};
static struct clk_regmap_phy_mux gcc_pcie_1_pipe_clk_src = {
.reg = 0xac07c,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_1_pipe_clk_src",
.parent_data = &(const struct clk_parent_data){
.index = DT_PCIE_1_PIPE_CLK,
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
};
static struct clk_regmap_phy_mux gcc_ufs_phy_rx_symbol_0_clk_src = {
.reg = 0x77068,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_phy_rx_symbol_0_clk_src",
.parent_data = &(const struct clk_parent_data){
.index = DT_UFS_PHY_RX_SYMBOL_0_CLK,
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
};
static struct clk_regmap_phy_mux gcc_ufs_phy_rx_symbol_1_clk_src = {
.reg = 0x770ec,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_phy_rx_symbol_1_clk_src",
.parent_data = &(const struct clk_parent_data){
.index = DT_UFS_PHY_RX_SYMBOL_1_CLK,
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
};
static struct clk_regmap_phy_mux gcc_ufs_phy_tx_symbol_0_clk_src = {
.reg = 0x77058,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_phy_tx_symbol_0_clk_src",
.parent_data = &(const struct clk_parent_data){
.index = DT_UFS_PHY_TX_SYMBOL_0_CLK,
},
.num_parents = 1,
.ops = &clk_regmap_phy_mux_ops,
},
},
};
static struct clk_regmap_mux gcc_usb3_prim_phy_pipe_clk_src = {
.reg = 0x39070,
.shift = 0,
.width = 2,
.parent_map = gcc_parent_map_8,
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb3_prim_phy_pipe_clk_src",
.parent_data = gcc_parent_data_8,
.num_parents = ARRAY_SIZE(gcc_parent_data_8),
.ops = &clk_regmap_mux_closest_ops,
},
},
};
static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
{ }
};
static struct clk_rcg2 gcc_gp1_clk_src = {
.cmd_rcgr = 0x64004,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_gp1_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_gp2_clk_src = {
.cmd_rcgr = 0x65004,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_gp2_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_gp3_clk_src = {
.cmd_rcgr = 0x66004,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_1,
.freq_tbl = ftbl_gcc_gp1_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_gp3_clk_src",
.parent_data = gcc_parent_data_1,
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
.cmd_rcgr = 0x6b084,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_0_aux_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_pcie_0_phy_rchng_clk_src[] = {
F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pcie_0_phy_rchng_clk_src = {
.cmd_rcgr = 0x6b068,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_0_phy_rchng_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
.cmd_rcgr = 0xac080,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_1_aux_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_pcie_1_phy_rchng_clk_src = {
.cmd_rcgr = 0xac064,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcie_0_phy_rchng_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_1_phy_rchng_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = {
F(60000000, P_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
{ }
};
static struct clk_rcg2 gcc_pdm2_clk_src = {
.cmd_rcgr = 0x33010,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pdm2_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pdm2_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_gcc_qupv3_wrap1_qspi_ref_clk_src[] = {
F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375),
F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375),
F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75),
F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625),
F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
F(250000000, P_GCC_GPLL7_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_init_data gcc_qupv3_wrap1_qspi_ref_clk_src_init = {
.name = "gcc_qupv3_wrap1_qspi_ref_clk_src",
.parent_data = gcc_parent_data_4,
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_no_init_park_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_qspi_ref_clk_src = {
.cmd_rcgr = 0x188c0,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_4,
.freq_tbl = ftbl_gcc_qupv3_wrap1_qspi_ref_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &gcc_qupv3_wrap1_qspi_ref_clk_src_init,
};
static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s0_clk_src[] = {
F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375),
F(61440000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 625),
F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375),
F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75),
F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625),
F(120000000, P_GCC_GPLL0_OUT_MAIN, 5, 0, 0),
{ }
};
static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
.name = "gcc_qupv3_wrap1_s0_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_no_init_park_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
.cmd_rcgr = 0x18014,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
.name = "gcc_qupv3_wrap1_s1_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_no_init_park_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
.cmd_rcgr = 0x18150,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init,
};
static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s3_clk_src[] = {
F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375),
F(61440000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 625),
F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
{ }
};
static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
.name = "gcc_qupv3_wrap1_s3_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_no_init_park_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
.cmd_rcgr = 0x182a0,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap1_s3_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
.name = "gcc_qupv3_wrap1_s4_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_no_init_park_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
.cmd_rcgr = 0x183dc,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init,
};
static const struct freq_tbl ftbl_gcc_qupv3_wrap1_s5_clk_src[] = {
F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375),
F(61440000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 625),
F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375),
F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75),
F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625),
F(128000000, P_GCC_GPLL0_OUT_MAIN, 1, 16, 75),
{ }
};
static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
.name = "gcc_qupv3_wrap1_s5_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_no_init_park_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
.cmd_rcgr = 0x18518,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap1_s5_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
.name = "gcc_qupv3_wrap1_s6_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_no_init_park_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
.cmd_rcgr = 0x18654,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap1_s3_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &gcc_qupv3_wrap1_s6_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {
.name = "gcc_qupv3_wrap1_s7_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_no_init_park_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
.cmd_rcgr = 0x18790,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap1_s3_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &gcc_qupv3_wrap1_s7_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
.name = "gcc_qupv3_wrap2_s0_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_no_init_park_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
.cmd_rcgr = 0x1e014,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
.name = "gcc_qupv3_wrap2_s1_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_no_init_park_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
.cmd_rcgr = 0x1e150,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init,
};
static const struct freq_tbl ftbl_gcc_qupv3_wrap2_s2_clk_src[] = {
F(7372800, P_GCC_GPLL0_OUT_EVEN, 1, 384, 15625),
F(14745600, P_GCC_GPLL0_OUT_EVEN, 1, 768, 15625),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(29491200, P_GCC_GPLL0_OUT_EVEN, 1, 1536, 15625),
F(32000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 75),
F(48000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 25),
F(51200000, P_GCC_GPLL0_OUT_EVEN, 1, 64, 375),
F(61440000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 625),
F(64000000, P_GCC_GPLL0_OUT_EVEN, 1, 16, 75),
F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
F(80000000, P_GCC_GPLL0_OUT_EVEN, 1, 4, 15),
F(96000000, P_GCC_GPLL0_OUT_EVEN, 1, 8, 25),
F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
F(102400000, P_GCC_GPLL0_OUT_EVEN, 1, 128, 375),
F(112000000, P_GCC_GPLL0_OUT_EVEN, 1, 28, 75),
F(117964800, P_GCC_GPLL0_OUT_EVEN, 1, 6144, 15625),
F(125000000, P_GCC_GPLL7_OUT_MAIN, 4, 0, 0),
{ }
};
static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
.name = "gcc_qupv3_wrap2_s2_clk_src",
.parent_data = gcc_parent_data_4,
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_no_init_park_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
.cmd_rcgr = 0x1e28c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_4,
.freq_tbl = ftbl_gcc_qupv3_wrap2_s2_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
.name = "gcc_qupv3_wrap2_s3_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_no_init_park_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
.cmd_rcgr = 0x1e3c8,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap1_s3_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
.name = "gcc_qupv3_wrap2_s4_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_no_init_park_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
.cmd_rcgr = 0x1e504,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap1_s0_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
.name = "gcc_qupv3_wrap2_s5_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_no_init_park_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
.cmd_rcgr = 0x1e640,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap1_s5_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = {
.name = "gcc_qupv3_wrap2_s6_clk_src",
.parent_data = gcc_parent_data_4,
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_no_init_park_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = {
.cmd_rcgr = 0x1e77c,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_4,
.freq_tbl = ftbl_gcc_qupv3_wrap1_s3_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &gcc_qupv3_wrap2_s6_clk_src_init,
};
static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_init = {
.name = "gcc_qupv3_wrap2_s7_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_no_init_park_ops,
};
static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = {
.cmd_rcgr = 0x1e8b8,
.mnd_width = 16,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_qupv3_wrap1_s3_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &gcc_qupv3_wrap2_s7_clk_src_init,
};
static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
F(144000, P_BI_TCXO, 16, 3, 25),
F(400000, P_BI_TCXO, 12, 1, 4),
F(20000000, P_GCC_GPLL0_OUT_EVEN, 5, 1, 3),
F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
F(192000000, P_GCC_GPLL8_OUT_MAIN, 2, 0, 0),
F(384000000, P_GCC_GPLL8_OUT_MAIN, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
.cmd_rcgr = 0xa9018,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_5,
.freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_sdcc1_apps_clk_src",
.parent_data = gcc_parent_data_5,
.num_parents = ARRAY_SIZE(gcc_parent_data_5),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_floor_ops,
},
};
static const struct freq_tbl ftbl_gcc_sdcc1_ice_core_clk_src[] = {
F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
F(150000000, P_GCC_GPLL0_OUT_EVEN, 2, 0, 0),
F(300000000, P_GCC_GPLL0_OUT_EVEN, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = {
.cmd_rcgr = 0xa9040,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_5,
.freq_tbl = ftbl_gcc_sdcc1_ice_core_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_sdcc1_ice_core_clk_src",
.parent_data = gcc_parent_data_5,
.num_parents = ARRAY_SIZE(gcc_parent_data_5),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_floor_ops,
},
};
static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
F(400000, P_BI_TCXO, 12, 1, 4),
F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
F(37500000, P_GCC_GPLL0_OUT_EVEN, 8, 0, 0),
F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
{ }
};
static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
.cmd_rcgr = 0x1401c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_7,
.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_sdcc2_apps_clk_src",
.parent_data = gcc_parent_data_7,
.num_parents = ARRAY_SIZE(gcc_parent_data_7),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_floor_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0),
F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
.cmd_rcgr = 0x77034,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_phy_axi_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_no_init_park_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
F(201500000, P_GCC_GPLL4_OUT_MAIN, 4, 0, 0),
F(403000000, P_GCC_GPLL4_OUT_MAIN, 2, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
.cmd_rcgr = 0x7708c,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_phy_ice_core_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_no_init_park_ops,
},
};
static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = {
F(9600000, P_BI_TCXO, 2, 0, 0),
F(19200000, P_BI_TCXO, 1, 0, 0),
{ }
};
static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
.cmd_rcgr = 0x770c0,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_6,
.freq_tbl = ftbl_gcc_ufs_phy_phy_aux_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_phy_phy_aux_clk_src",
.parent_data = gcc_parent_data_6,
.num_parents = ARRAY_SIZE(gcc_parent_data_6),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_no_init_park_ops,
},
};
static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
.cmd_rcgr = 0x770a4,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_2,
.freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_phy_unipro_core_clk_src",
.parent_data = gcc_parent_data_2,
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_no_init_park_ops,
},
};
static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
F(66666667, P_GCC_GPLL0_OUT_EVEN, 4.5, 0, 0),
F(133333333, P_GCC_GPLL0_OUT_MAIN, 4.5, 0, 0),
F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
F(240000000, P_GCC_GPLL0_OUT_MAIN, 2.5, 0, 0),
{ }
};
static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
.cmd_rcgr = 0x39030,
.mnd_width = 8,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_usb30_prim_master_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_prim_master_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
.cmd_rcgr = 0x39048,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_0,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_prim_mock_utmi_clk_src",
.parent_data = gcc_parent_data_0,
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
.cmd_rcgr = 0x39074,
.mnd_width = 0,
.hid_width = 5,
.parent_map = gcc_parent_map_3,
.freq_tbl = ftbl_gcc_pcie_0_aux_clk_src,
.hw_clk_ctrl = true,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb3_prim_phy_aux_clk_src",
.parent_data = gcc_parent_data_3,
.num_parents = ARRAY_SIZE(gcc_parent_data_3),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_regmap_div gcc_pcie_0_pipe_div2_clk_src = {
.reg = 0x6b0a4,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_0_pipe_div2_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_0_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gcc_pcie_1_pipe_div2_clk_src = {
.reg = 0xac0a0,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_1_pipe_div2_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_1_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gcc_qupv3_wrap1_s2_clk_src = {
.reg = 0x1828c,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap1_s2_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_qspi_ref_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = {
.reg = 0x39060,
.shift = 0,
.width = 4,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_prim_mock_utmi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_regmap_div_ro_ops,
},
};
static struct clk_branch gcc_aggre_noc_pcie_axi_clk = {
.halt_reg = 0x10068,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x10068,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(30),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_aggre_noc_pcie_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_ufs_phy_axi_clk = {
.halt_reg = 0x770f4,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x770f4,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x770f4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_aggre_ufs_phy_axi_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_ufs_phy_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_aggre_usb3_prim_axi_clk = {
.halt_reg = 0x39094,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x39094,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_aggre_usb3_prim_axi_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_prim_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_boot_rom_ahb_clk = {
.halt_reg = 0x38004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x38004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(10),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_boot_rom_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camera_hf_axi_clk = {
.halt_reg = 0x26014,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x26014,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x26014,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_camera_hf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_camera_sf_axi_clk = {
.halt_reg = 0x26024,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x26024,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x26024,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_camera_sf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cfg_noc_pcie_anoc_ahb_clk = {
.halt_reg = 0x10050,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x10050,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(20),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_cfg_noc_pcie_anoc_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = {
.halt_reg = 0x39090,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x39090,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_cfg_noc_usb3_prim_axi_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_prim_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_cnoc_pcie_sf_axi_clk = {
.halt_reg = 0x10058,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x10058,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(6),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_cnoc_pcie_sf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ddrss_gpu_axi_clk = {
.halt_reg = 0x71158,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x71158,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x71158,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ddrss_gpu_axi_clk",
.ops = &clk_branch2_aon_ops,
},
},
};
static struct clk_branch gcc_ddrss_pcie_sf_qtb_clk = {
.halt_reg = 0x1007c,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x1007c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(19),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ddrss_pcie_sf_qtb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_disp_hf_axi_clk = {
.halt_reg = 0x27008,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x27008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_disp_hf_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp1_clk = {
.halt_reg = 0x64000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x64000,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gp1_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_gp1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp2_clk = {
.halt_reg = 0x65000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x65000,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gp2_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_gp2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gp3_clk = {
.halt_reg = 0x66000,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x66000,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gp3_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_gp3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_gemnoc_gfx_clk = {
.halt_reg = 0x71010,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x71010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x71010,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gpu_gemnoc_gfx_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_gpll0_cph_clk_src = {
.halt_reg = 0x71150,
.halt_check = BRANCH_HALT_ENABLE_VOTED,
.clkr = {
.enable_reg = 0x71150,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gpu_gpll0_cph_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gcc_gpll0.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_gpll0_div_cph_clk_src = {
.halt_reg = 0x71154,
.halt_check = BRANCH_HALT_ENABLE_VOTED,
.clkr = {
.enable_reg = 0x71154,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gpu_gpll0_div_cph_clk_src",
.parent_hws = (const struct clk_hw*[]) {
&gcc_gpll0_out_even.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_gpu_smmu_vote_clk = {
.halt_reg = 0x7d000,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7d000,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_gpu_smmu_vote_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_mmu_tcu_vote_clk = {
.halt_reg = 0x7d02c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x7d02c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_mmu_tcu_vote_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_aux_clk = {
.halt_reg = 0x6b044,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(3),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_0_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_0_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
.halt_reg = 0x6b040,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x6b040,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(2),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_0_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
.halt_reg = 0x6b030,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x6b030,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(1),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_0_mstr_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_phy_rchng_clk = {
.halt_reg = 0x6b064,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(22),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_0_phy_rchng_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_0_phy_rchng_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_pipe_clk = {
.halt_reg = 0x6b054,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(4),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_0_pipe_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_0_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_pipe_div2_clk = {
.halt_reg = 0x6b0a8,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(13),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_0_pipe_div2_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_0_pipe_div2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_slv_axi_clk = {
.halt_reg = 0x6b020,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x6b020,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_0_slv_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = {
.halt_reg = 0x6b01c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(5),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_0_slv_q2a_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_aux_clk = {
.halt_reg = 0xac040,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(29),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_1_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_1_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
.halt_reg = 0xac03c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0xac03c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(28),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_1_cfg_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
.halt_reg = 0xac02c,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0xac02c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(27),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_1_mstr_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_phy_rchng_clk = {
.halt_reg = 0xac060,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(24),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_1_phy_rchng_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_1_phy_rchng_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_pipe_clk = {
.halt_reg = 0xac050,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(23),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_1_pipe_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_1_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_pipe_div2_clk = {
.halt_reg = 0xac0a4,
.halt_check = BRANCH_HALT_SKIP,
.clkr = {
.enable_reg = 0x52018,
.enable_mask = BIT(15),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_1_pipe_div2_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pcie_1_pipe_div2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_slv_axi_clk = {
.halt_reg = 0xac01c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0xac01c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(26),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_1_slv_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = {
.halt_reg = 0xac018,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(25),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pcie_1_slv_q2a_axi_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm2_clk = {
.halt_reg = 0x3300c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3300c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pdm2_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_pdm2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_ahb_clk = {
.halt_reg = 0x33004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x33004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x33004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pdm_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_pdm_xo4_clk = {
.halt_reg = 0x33008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x33008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_pdm_xo4_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_camera_cmd_ahb_clk = {
.halt_reg = 0x26010,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x26010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x26010,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qmip_camera_cmd_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = {
.halt_reg = 0x26008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x26008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x26008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qmip_camera_nrt_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_camera_rt_ahb_clk = {
.halt_reg = 0x2600c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x2600c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x2600c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qmip_camera_rt_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_gpu_ahb_clk = {
.halt_reg = 0x71008,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x71008,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x71008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qmip_gpu_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_pcie_ahb_clk = {
.halt_reg = 0x6b018,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x6b018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52000,
.enable_mask = BIT(11),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qmip_pcie_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_video_v_cpu_ahb_clk = {
.halt_reg = 0x32010,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x32010,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x32010,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qmip_video_v_cpu_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = {
.halt_reg = 0x3200c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x3200c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x3200c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qmip_video_vcodec_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = {
.halt_reg = 0x2301c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(18),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap1_core_2x_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_core_clk = {
.halt_reg = 0x23008,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(19),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap1_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_qspi_ref_clk = {
.halt_reg = 0x188bc,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(29),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap1_qspi_ref_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_qspi_ref_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s0_clk = {
.halt_reg = 0x18004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(22),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap1_s0_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_s0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s1_clk = {
.halt_reg = 0x18140,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(23),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap1_s1_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_s1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s2_clk = {
.halt_reg = 0x1827c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(24),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap1_s2_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_s2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s3_clk = {
.halt_reg = 0x18290,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(25),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap1_s3_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_s3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s4_clk = {
.halt_reg = 0x183cc,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(26),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap1_s4_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_s4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s5_clk = {
.halt_reg = 0x18508,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(27),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap1_s5_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_s5_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s6_clk = {
.halt_reg = 0x18644,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(28),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap1_s6_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_s6_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap1_s7_clk = {
.halt_reg = 0x18780,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(16),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap1_s7_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap1_s7_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = {
.halt_reg = 0x23174,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(3),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap2_core_2x_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_core_clk = {
.halt_reg = 0x23160,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap2_core_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s0_clk = {
.halt_reg = 0x1e004,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(4),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap2_s0_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap2_s0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s1_clk = {
.halt_reg = 0x1e140,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(5),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap2_s1_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap2_s1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s2_clk = {
.halt_reg = 0x1e27c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(6),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap2_s2_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap2_s2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s3_clk = {
.halt_reg = 0x1e3b8,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(7),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap2_s3_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap2_s3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s4_clk = {
.halt_reg = 0x1e4f4,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(8),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap2_s4_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap2_s4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s5_clk = {
.halt_reg = 0x1e630,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(9),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap2_s5_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap2_s5_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s6_clk = {
.halt_reg = 0x1e76c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(10),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap2_s6_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap2_s6_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap2_s7_clk = {
.halt_reg = 0x1e8a8,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(17),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap2_s7_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_qupv3_wrap2_s7_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = {
.halt_reg = 0x23000,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(20),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap_1_m_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = {
.halt_reg = 0x23004,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x23004,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52008,
.enable_mask = BIT(21),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap_1_s_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = {
.halt_reg = 0x23158,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x23158,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(2),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap_2_m_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = {
.halt_reg = 0x2315c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x2315c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x52010,
.enable_mask = BIT(1),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_qupv3_wrap_2_s_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_ahb_clk = {
.halt_reg = 0xa9004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa9004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_sdcc1_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_apps_clk = {
.halt_reg = 0xa9008,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0xa9008,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_sdcc1_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_sdcc1_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc1_ice_core_clk = {
.halt_reg = 0xa9030,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0xa9030,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0xa9030,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_sdcc1_ice_core_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_sdcc1_ice_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_ahb_clk = {
.halt_reg = 0x14014,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x14014,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_sdcc2_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_sdcc2_apps_clk = {
.halt_reg = 0x14004,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x14004,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_sdcc2_apps_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_sdcc2_apps_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_ahb_clk = {
.halt_reg = 0x77028,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x77028,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77028,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_phy_ahb_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_axi_clk = {
.halt_reg = 0x77018,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x77018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x77018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_phy_axi_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_ufs_phy_axi_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_ice_core_clk = {
.halt_reg = 0x7707c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x7707c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7707c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_phy_ice_core_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
.halt_reg = 0x770bc,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x770bc,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x770bc,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_phy_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
.halt_reg = 0x77030,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x77030,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_phy_rx_symbol_0_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_ufs_phy_rx_symbol_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
.halt_reg = 0x770d8,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x770d8,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_phy_rx_symbol_1_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_ufs_phy_rx_symbol_1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
.halt_reg = 0x7702c,
.halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x7702c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_phy_tx_symbol_0_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_ufs_phy_tx_symbol_0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
.halt_reg = 0x7706c,
.halt_check = BRANCH_HALT_VOTED,
.hwcg_reg = 0x7706c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x7706c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_ufs_phy_unipro_core_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_atb_clk = {
.halt_reg = 0x3908c,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x3908c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_prim_atb_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_prim_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_master_clk = {
.halt_reg = 0x39018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x39018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_prim_master_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_prim_master_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_mock_utmi_clk = {
.halt_reg = 0x3902c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x3902c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_prim_mock_utmi_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb30_prim_sleep_clk = {
.halt_reg = 0x39028,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x39028,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb30_prim_sleep_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_phy_aux_clk = {
.halt_reg = 0x39064,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x39064,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb3_prim_phy_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = {
.halt_reg = 0x39068,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x39068,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb3_prim_phy_com_aux_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb3_prim_phy_aux_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
.halt_reg = 0x3906c,
.halt_check = BRANCH_HALT_DELAY,
.hwcg_reg = 0x3906c,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x3906c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_usb3_prim_phy_pipe_clk",
.parent_hws = (const struct clk_hw*[]) {
&gcc_usb3_prim_phy_pipe_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_axi0_clk = {
.halt_reg = 0x32018,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x32018,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x32018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_video_axi0_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch gcc_video_axi1_clk = {
.halt_reg = 0x32028,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0x32028,
.hwcg_bit = 1,
.clkr = {
.enable_reg = 0x32028,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "gcc_video_axi1_clk",
.ops = &clk_branch2_ops,
},
},
};
static struct gdsc gcc_pcie_0_gdsc = {
.gdscr = 0x6b004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.collapse_ctrl = 0x5214c,
.collapse_mask = BIT(0),
.pd = {
.name = "gcc_pcie_0_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
};
static struct gdsc gcc_pcie_0_phy_gdsc = {
.gdscr = 0x6c000,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0x2,
.collapse_ctrl = 0x5214c,
.collapse_mask = BIT(2),
.pd = {
.name = "gcc_pcie_0_phy_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
};
static struct gdsc gcc_pcie_1_gdsc = {
.gdscr = 0xac004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.collapse_ctrl = 0x5214c,
.collapse_mask = BIT(3),
.pd = {
.name = "gcc_pcie_1_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
};
static struct gdsc gcc_pcie_1_phy_gdsc = {
.gdscr = 0xad000,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0x2,
.collapse_ctrl = 0x5214c,
.collapse_mask = BIT(4),
.pd = {
.name = "gcc_pcie_1_phy_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | VOTABLE,
};
static struct gdsc gcc_ufs_mem_phy_gdsc = {
.gdscr = 0x9e000,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0x2,
.pd = {
.name = "gcc_ufs_mem_phy_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct gdsc gcc_ufs_phy_gdsc = {
.gdscr = 0x77004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "gcc_ufs_phy_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct gdsc gcc_usb30_prim_gdsc = {
.gdscr = 0x39004,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0xf,
.pd = {
.name = "gcc_usb30_prim_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct gdsc gcc_usb3_phy_gdsc = {
.gdscr = 0x50018,
.en_rest_wait_val = 0x2,
.en_few_wait_val = 0x2,
.clk_dis_wait_val = 0x2,
.pd = {
.name = "gcc_usb3_phy_gdsc",
},
.pwrsts = PWRSTS_OFF_ON,
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
};
static struct clk_regmap *gcc_eliza_clocks[] = {
[GCC_AGGRE_NOC_PCIE_AXI_CLK] = &gcc_aggre_noc_pcie_axi_clk.clkr,
[GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
[GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
[GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
[GCC_CAMERA_HF_AXI_CLK] = &gcc_camera_hf_axi_clk.clkr,
[GCC_CAMERA_SF_AXI_CLK] = &gcc_camera_sf_axi_clk.clkr,
[GCC_CFG_NOC_PCIE_ANOC_AHB_CLK] = &gcc_cfg_noc_pcie_anoc_ahb_clk.clkr,
[GCC_CFG_NOC_USB3_PRIM_AXI_CLK] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr,
[GCC_CNOC_PCIE_SF_AXI_CLK] = &gcc_cnoc_pcie_sf_axi_clk.clkr,
[GCC_DDRSS_GPU_AXI_CLK] = &gcc_ddrss_gpu_axi_clk.clkr,
[GCC_DDRSS_PCIE_SF_QTB_CLK] = &gcc_ddrss_pcie_sf_qtb_clk.clkr,
[GCC_DISP_HF_AXI_CLK] = &gcc_disp_hf_axi_clk.clkr,
[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,
[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
[GCC_GPLL0] = &gcc_gpll0.clkr,
[GCC_GPLL0_OUT_EVEN] = &gcc_gpll0_out_even.clkr,
[GCC_GPLL4] = &gcc_gpll4.clkr,
[GCC_GPLL7] = &gcc_gpll7.clkr,
[GCC_GPLL8] = &gcc_gpll8.clkr,
[GCC_GPLL9] = &gcc_gpll9.clkr,
[GCC_GPU_GEMNOC_GFX_CLK] = &gcc_gpu_gemnoc_gfx_clk.clkr,
[GCC_GPU_GPLL0_CPH_CLK_SRC] = &gcc_gpu_gpll0_cph_clk_src.clkr,
[GCC_GPU_GPLL0_DIV_CPH_CLK_SRC] = &gcc_gpu_gpll0_div_cph_clk_src.clkr,
[GCC_GPU_SMMU_VOTE_CLK] = &gcc_gpu_smmu_vote_clk.clkr,
[GCC_MMU_TCU_VOTE_CLK] = &gcc_mmu_tcu_vote_clk.clkr,
[GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
[GCC_PCIE_0_AUX_CLK_SRC] = &gcc_pcie_0_aux_clk_src.clkr,
[GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
[GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
[GCC_PCIE_0_PHY_RCHNG_CLK] = &gcc_pcie_0_phy_rchng_clk.clkr,
[GCC_PCIE_0_PHY_RCHNG_CLK_SRC] = &gcc_pcie_0_phy_rchng_clk_src.clkr,
[GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
[GCC_PCIE_0_PIPE_CLK_SRC] = &gcc_pcie_0_pipe_clk_src.clkr,
[GCC_PCIE_0_PIPE_DIV2_CLK] = &gcc_pcie_0_pipe_div2_clk.clkr,
[GCC_PCIE_0_PIPE_DIV2_CLK_SRC] = &gcc_pcie_0_pipe_div2_clk_src.clkr,
[GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
[GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
[GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
[GCC_PCIE_1_AUX_CLK_SRC] = &gcc_pcie_1_aux_clk_src.clkr,
[GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
[GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
[GCC_PCIE_1_PHY_RCHNG_CLK] = &gcc_pcie_1_phy_rchng_clk.clkr,
[GCC_PCIE_1_PHY_RCHNG_CLK_SRC] = &gcc_pcie_1_phy_rchng_clk_src.clkr,
[GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
[GCC_PCIE_1_PIPE_CLK_SRC] = &gcc_pcie_1_pipe_clk_src.clkr,
[GCC_PCIE_1_PIPE_DIV2_CLK] = &gcc_pcie_1_pipe_div2_clk.clkr,
[GCC_PCIE_1_PIPE_DIV2_CLK_SRC] = &gcc_pcie_1_pipe_div2_clk_src.clkr,
[GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
[GCC_PCIE_1_SLV_Q2A_AXI_CLK] = &gcc_pcie_1_slv_q2a_axi_clk.clkr,
[GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
[GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr,
[GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
[GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr,
[GCC_QMIP_CAMERA_CMD_AHB_CLK] = &gcc_qmip_camera_cmd_ahb_clk.clkr,
[GCC_QMIP_CAMERA_NRT_AHB_CLK] = &gcc_qmip_camera_nrt_ahb_clk.clkr,
[GCC_QMIP_CAMERA_RT_AHB_CLK] = &gcc_qmip_camera_rt_ahb_clk.clkr,
[GCC_QMIP_GPU_AHB_CLK] = &gcc_qmip_gpu_ahb_clk.clkr,
[GCC_QMIP_PCIE_AHB_CLK] = &gcc_qmip_pcie_ahb_clk.clkr,
[GCC_QMIP_VIDEO_V_CPU_AHB_CLK] = &gcc_qmip_video_v_cpu_ahb_clk.clkr,
[GCC_QMIP_VIDEO_VCODEC_AHB_CLK] = &gcc_qmip_video_vcodec_ahb_clk.clkr,
[GCC_QUPV3_WRAP1_CORE_2X_CLK] = &gcc_qupv3_wrap1_core_2x_clk.clkr,
[GCC_QUPV3_WRAP1_CORE_CLK] = &gcc_qupv3_wrap1_core_clk.clkr,
[GCC_QUPV3_WRAP1_QSPI_REF_CLK] = &gcc_qupv3_wrap1_qspi_ref_clk.clkr,
[GCC_QUPV3_WRAP1_QSPI_REF_CLK_SRC] = &gcc_qupv3_wrap1_qspi_ref_clk_src.clkr,
[GCC_QUPV3_WRAP1_S0_CLK] = &gcc_qupv3_wrap1_s0_clk.clkr,
[GCC_QUPV3_WRAP1_S0_CLK_SRC] = &gcc_qupv3_wrap1_s0_clk_src.clkr,
[GCC_QUPV3_WRAP1_S1_CLK] = &gcc_qupv3_wrap1_s1_clk.clkr,
[GCC_QUPV3_WRAP1_S1_CLK_SRC] = &gcc_qupv3_wrap1_s1_clk_src.clkr,
[GCC_QUPV3_WRAP1_S2_CLK] = &gcc_qupv3_wrap1_s2_clk.clkr,
[GCC_QUPV3_WRAP1_S2_CLK_SRC] = &gcc_qupv3_wrap1_s2_clk_src.clkr,
[GCC_QUPV3_WRAP1_S3_CLK] = &gcc_qupv3_wrap1_s3_clk.clkr,
[GCC_QUPV3_WRAP1_S3_CLK_SRC] = &gcc_qupv3_wrap1_s3_clk_src.clkr,
[GCC_QUPV3_WRAP1_S4_CLK] = &gcc_qupv3_wrap1_s4_clk.clkr,
[GCC_QUPV3_WRAP1_S4_CLK_SRC] = &gcc_qupv3_wrap1_s4_clk_src.clkr,
[GCC_QUPV3_WRAP1_S5_CLK] = &gcc_qupv3_wrap1_s5_clk.clkr,
[GCC_QUPV3_WRAP1_S5_CLK_SRC] = &gcc_qupv3_wrap1_s5_clk_src.clkr,
[GCC_QUPV3_WRAP1_S6_CLK] = &gcc_qupv3_wrap1_s6_clk.clkr,
[GCC_QUPV3_WRAP1_S6_CLK_SRC] = &gcc_qupv3_wrap1_s6_clk_src.clkr,
[GCC_QUPV3_WRAP1_S7_CLK] = &gcc_qupv3_wrap1_s7_clk.clkr,
[GCC_QUPV3_WRAP1_S7_CLK_SRC] = &gcc_qupv3_wrap1_s7_clk_src.clkr,
[GCC_QUPV3_WRAP2_CORE_2X_CLK] = &gcc_qupv3_wrap2_core_2x_clk.clkr,
[GCC_QUPV3_WRAP2_CORE_CLK] = &gcc_qupv3_wrap2_core_clk.clkr,
[GCC_QUPV3_WRAP2_S0_CLK] = &gcc_qupv3_wrap2_s0_clk.clkr,
[GCC_QUPV3_WRAP2_S0_CLK_SRC] = &gcc_qupv3_wrap2_s0_clk_src.clkr,
[GCC_QUPV3_WRAP2_S1_CLK] = &gcc_qupv3_wrap2_s1_clk.clkr,
[GCC_QUPV3_WRAP2_S1_CLK_SRC] = &gcc_qupv3_wrap2_s1_clk_src.clkr,
[GCC_QUPV3_WRAP2_S2_CLK] = &gcc_qupv3_wrap2_s2_clk.clkr,
[GCC_QUPV3_WRAP2_S2_CLK_SRC] = &gcc_qupv3_wrap2_s2_clk_src.clkr,
[GCC_QUPV3_WRAP2_S3_CLK] = &gcc_qupv3_wrap2_s3_clk.clkr,
[GCC_QUPV3_WRAP2_S3_CLK_SRC] = &gcc_qupv3_wrap2_s3_clk_src.clkr,
[GCC_QUPV3_WRAP2_S4_CLK] = &gcc_qupv3_wrap2_s4_clk.clkr,
[GCC_QUPV3_WRAP2_S4_CLK_SRC] = &gcc_qupv3_wrap2_s4_clk_src.clkr,
[GCC_QUPV3_WRAP2_S5_CLK] = &gcc_qupv3_wrap2_s5_clk.clkr,
[GCC_QUPV3_WRAP2_S5_CLK_SRC] = &gcc_qupv3_wrap2_s5_clk_src.clkr,
[GCC_QUPV3_WRAP2_S6_CLK] = &gcc_qupv3_wrap2_s6_clk.clkr,
[GCC_QUPV3_WRAP2_S6_CLK_SRC] = &gcc_qupv3_wrap2_s6_clk_src.clkr,
[GCC_QUPV3_WRAP2_S7_CLK] = &gcc_qupv3_wrap2_s7_clk.clkr,
[GCC_QUPV3_WRAP2_S7_CLK_SRC] = &gcc_qupv3_wrap2_s7_clk_src.clkr,
[GCC_QUPV3_WRAP_1_M_AHB_CLK] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr,
[GCC_QUPV3_WRAP_1_S_AHB_CLK] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr,
[GCC_QUPV3_WRAP_2_M_AHB_CLK] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr,
[GCC_QUPV3_WRAP_2_S_AHB_CLK] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr,
[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
[GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,
[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
[GCC_SDCC1_ICE_CORE_CLK_SRC] = &gcc_sdcc1_ice_core_clk_src.clkr,
[GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
[GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
[GCC_SDCC2_APPS_CLK_SRC] = &gcc_sdcc2_apps_clk_src.clkr,
[GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
[GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
[GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
[GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
[GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
[GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
[GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
[GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
[GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr,
[GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
[GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC] = &gcc_ufs_phy_rx_symbol_1_clk_src.clkr,
[GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
[GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr,
[GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
[GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr,
[GCC_USB30_PRIM_ATB_CLK] = &gcc_usb30_prim_atb_clk.clkr,
[GCC_USB30_PRIM_MASTER_CLK] = &gcc_usb30_prim_master_clk.clkr,
[GCC_USB30_PRIM_MASTER_CLK_SRC] = &gcc_usb30_prim_master_clk_src.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_CLK] = &gcc_usb30_prim_mock_utmi_clk.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC] = &gcc_usb30_prim_mock_utmi_clk_src.clkr,
[GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr,
[GCC_USB30_PRIM_SLEEP_CLK] = &gcc_usb30_prim_sleep_clk.clkr,
[GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
[GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
[GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
[GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr,
[GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
[GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
};
static struct gdsc *gcc_eliza_gdscs[] = {
[GCC_PCIE_0_GDSC] = &gcc_pcie_0_gdsc,
[GCC_PCIE_0_PHY_GDSC] = &gcc_pcie_0_phy_gdsc,
[GCC_PCIE_1_GDSC] = &gcc_pcie_1_gdsc,
[GCC_PCIE_1_PHY_GDSC] = &gcc_pcie_1_phy_gdsc,
[GCC_UFS_MEM_PHY_GDSC] = &gcc_ufs_mem_phy_gdsc,
[GCC_UFS_PHY_GDSC] = &gcc_ufs_phy_gdsc,
[GCC_USB30_PRIM_GDSC] = &gcc_usb30_prim_gdsc,
[GCC_USB3_PHY_GDSC] = &gcc_usb3_phy_gdsc,
};
static const struct qcom_reset_map gcc_eliza_resets[] = {
[GCC_CAMERA_BCR] = { 0x26000 },
[GCC_DISPLAY_BCR] = { 0x27000 },
[GCC_GPU_BCR] = { 0x71000 },
[GCC_PCIE_0_BCR] = { 0x6b000 },
[GCC_PCIE_0_LINK_DOWN_BCR] = { 0x6c014 },
[GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0x6c020 },
[GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
[GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0x6c028 },
[GCC_PCIE_1_BCR] = { 0xac000 },
[GCC_PCIE_1_LINK_DOWN_BCR] = { 0x8e014 },
[GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0x8e020 },
[GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
[GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0x8e024 },
[GCC_PCIE_PHY_BCR] = { 0x6f000 },
[GCC_PCIE_PHY_CFG_AHB_BCR] = { 0x6f00c },
[GCC_PCIE_PHY_COM_BCR] = { 0x6f010 },
[GCC_PCIE_RSCC_BCR] = { 0x11000 },
[GCC_PDM_BCR] = { 0x33000 },
[GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
[GCC_QUPV3_WRAPPER_2_BCR] = { 0x1e000 },
[GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
[GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
[GCC_SDCC1_BCR] = { 0xa9000 },
[GCC_SDCC2_BCR] = { 0x14000 },
[GCC_UFS_PHY_BCR] = { 0x77000 },
[GCC_USB30_PRIM_BCR] = { 0x39000 },
[GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
[GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
[GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
[GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
[GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
[GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
[GCC_VIDEO_AXI0_CLK_ARES] = { 0x32018, 2 },
[GCC_VIDEO_AXI1_CLK_ARES] = { 0x32028, 2 },
[GCC_VIDEO_BCR] = { 0x32000 },
};
static const u32 gcc_eliza_critical_cbcrs[] = {
0xa0004, /* GCC_CAM_BIST_MCLK_AHB_CLK */
0x26004, /* GCC_CAMERA_AHB_CLK */
0x26034, /* GCC_CAMERA_XO_CLK */
0x27004, /* GCC_DISP_AHB_CLK */
0x71004, /* GCC_GPU_CFG_AHB_CLK */
0x52010, /* GCC_PCIE_RSCC_CFG_AHB_CLK */
0x52010, /* GCC_PCIE_RSCC_XO_CLK */
0x32004, /* GCC_VIDEO_AHB_CLK */
0x32038, /* GCC_VIDEO_XO_CLK */
};
static const struct clk_rcg_dfs_data gcc_eliza_dfs_clocks[] = {
DEFINE_RCG_DFS(gcc_qupv3_wrap1_qspi_ref_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s0_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s1_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s3_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s4_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s5_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s6_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap1_s7_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s0_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s1_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s2_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s3_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s4_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s5_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s6_clk_src),
DEFINE_RCG_DFS(gcc_qupv3_wrap2_s7_clk_src),
};
static const struct regmap_config gcc_eliza_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x1f41f0,
.fast_io = true,
};
static void clk_eliza_regs_configure(struct device *dev, struct regmap *regmap)
{
/* FORCE_MEM_CORE_ON for ufs phy ice core and gcc ufs phy axi clocks */
qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_axi_clk, true);
}
static const struct qcom_cc_driver_data gcc_eliza_driver_data = {
.clk_cbcrs = gcc_eliza_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(gcc_eliza_critical_cbcrs),
.dfs_rcgs = gcc_eliza_dfs_clocks,
.num_dfs_rcgs = ARRAY_SIZE(gcc_eliza_dfs_clocks),
.clk_regs_configure = clk_eliza_regs_configure,
};
static const struct qcom_cc_desc gcc_eliza_desc = {
.config = &gcc_eliza_regmap_config,
.clks = gcc_eliza_clocks,
.num_clks = ARRAY_SIZE(gcc_eliza_clocks),
.resets = gcc_eliza_resets,
.num_resets = ARRAY_SIZE(gcc_eliza_resets),
.gdscs = gcc_eliza_gdscs,
.num_gdscs = ARRAY_SIZE(gcc_eliza_gdscs),
.driver_data = &gcc_eliza_driver_data,
};
static const struct of_device_id gcc_eliza_match_table[] = {
{ .compatible = "qcom,eliza-gcc" },
{ }
};
MODULE_DEVICE_TABLE(of, gcc_eliza_match_table);
static int gcc_eliza_probe(struct platform_device *pdev)
{
return qcom_cc_probe(pdev, &gcc_eliza_desc);
}
static struct platform_driver gcc_eliza_driver = {
.probe = gcc_eliza_probe,
.driver = {
.name = "gcc-eliza",
.of_match_table = gcc_eliza_match_table,
},
};
static int __init gcc_eliza_init(void)
{
return platform_driver_register(&gcc_eliza_driver);
}
subsys_initcall(gcc_eliza_init);
static void __exit gcc_eliza_exit(void)
{
platform_driver_unregister(&gcc_eliza_driver);
}
module_exit(gcc_eliza_exit);
MODULE_DESCRIPTION("QTI GCC Eliza Driver");
MODULE_LICENSE("GPL");