| # SPDX-License-Identifier: GPL-2.0 | |
| config CLK_INTEL_SOCFPGA | |
| bool "Intel SoCFPGA family clock support" if COMPILE_TEST && !ARCH_INTEL_SOCFPGA | |
| default ARCH_INTEL_SOCFPGA | |
| help | |
| Support for the clock controllers present on Intel SoCFPGA and eASIC | |
| devices like Aria, Cyclone, Stratix 10, Agilex and N5X eASIC. | |
| if CLK_INTEL_SOCFPGA | |
| config CLK_INTEL_SOCFPGA32 | |
| bool "Intel Aria / Cyclone clock controller support" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA) | |
| default ARM && ARCH_INTEL_SOCFPGA | |
| config CLK_INTEL_SOCFPGA64 | |
| bool "Intel Stratix / Agilex / N5X / Agilex5 clock controller support" if COMPILE_TEST && (!ARM64 || !ARCH_INTEL_SOCFPGA) | |
| default ARM64 && ARCH_INTEL_SOCFPGA | |
| endif # CLK_INTEL_SOCFPGA |