| # SPDX-License-Identifier: GPL-2.0 | |
| config USB_DWC3 | |
| tristate "DesignWare USB3 DRD Core Support" | |
| depends on (USB || USB_GADGET) && HAS_DMA | |
| depends on (EXTCON || EXTCON=n) | |
| select USB_XHCI_PLATFORM if USB_XHCI_HCD | |
| select USB_ROLE_SWITCH if USB_DWC3_DUAL_ROLE | |
| help | |
| Say Y or M here if your system has a Dual Role SuperSpeed | |
| USB controller based on the DesignWare USB3 IP Core. | |
| If you choose to build this driver as a dynamically linked | |
| module, the module will be called dwc3.ko. | |
| if USB_DWC3 | |
| config USB_DWC3_ULPI | |
| bool "Register ULPI PHY Interface" | |
| depends on USB_ULPI_BUS=y || USB_ULPI_BUS=USB_DWC3 | |
| help | |
| Select this if you have ULPI type PHY attached to your DWC3 | |
| controller. | |
| choice | |
| prompt "DWC3 Mode Selection" | |
| default USB_DWC3_DUAL_ROLE if (USB && USB_GADGET) | |
| default USB_DWC3_HOST if (USB && !USB_GADGET) | |
| default USB_DWC3_GADGET if (!USB && USB_GADGET) | |
| config USB_DWC3_HOST | |
| bool "Host only mode" | |
| depends on USB=y || USB=USB_DWC3 | |
| help | |
| Select this when you want to use DWC3 in host mode only, | |
| thereby the gadget feature will be regressed. | |
| config USB_DWC3_GADGET | |
| bool "Gadget only mode" | |
| depends on USB_GADGET=y || USB_GADGET=USB_DWC3 | |
| help | |
| Select this when you want to use DWC3 in gadget mode only, | |
| thereby the host feature will be regressed. | |
| config USB_DWC3_DUAL_ROLE | |
| bool "Dual Role mode" | |
| depends on ((USB=y || USB=USB_DWC3) && (USB_GADGET=y || USB_GADGET=USB_DWC3)) | |
| help | |
| This is the default mode of working of DWC3 controller where | |
| both host and gadget features are enabled. | |
| endchoice | |
| comment "Platform Glue Driver Support" | |
| config USB_DWC3_OMAP | |
| tristate "Texas Instruments OMAP5 and similar Platforms" | |
| depends on ARCH_OMAP2PLUS || COMPILE_TEST | |
| depends on EXTCON || !EXTCON | |
| depends on OF | |
| default USB_DWC3 | |
| help | |
| Some platforms from Texas Instruments like OMAP5, DRA7xxx and | |
| AM437x use this IP for USB2/3 functionality. | |
| Say 'Y' or 'M' here if you have one such device | |
| config USB_DWC3_EXYNOS | |
| tristate "Samsung Exynos SoC Platform" | |
| depends on (ARCH_EXYNOS || COMPILE_TEST) && OF | |
| default USB_DWC3 | |
| help | |
| Recent Samsung Exynos SoCs (Exynos5250, Exynos5410, Exynos542x, | |
| Exynos5800, Exynos5433, Exynos7) ship with one DesignWare Core USB3 | |
| IP inside, say 'Y' or 'M' if you have one such device. | |
| config USB_DWC3_PCI | |
| tristate "PCIe-based Platforms" | |
| depends on USB_PCI && ACPI | |
| default USB_DWC3 | |
| help | |
| If you're using the DesignWare Core IP with a PCIe (but not HAPS | |
| platform), please say 'Y' or 'M' here. | |
| config USB_DWC3_HAPS | |
| tristate "Synopsys PCIe-based HAPS Platforms" | |
| depends on USB_PCI | |
| default USB_DWC3 | |
| help | |
| If you're using the DesignWare Core IP with a Synopsys PCIe HAPS | |
| platform, please say 'Y' or 'M' here. | |
| config USB_DWC3_KEYSTONE | |
| tristate "Texas Instruments Keystone2/AM654 Platforms" | |
| depends on ARCH_KEYSTONE || ARCH_K3 || COMPILE_TEST | |
| default USB_DWC3 | |
| help | |
| Support of USB2/3 functionality in TI Keystone2 and AM654 platforms. | |
| Say 'Y' or 'M' here if you have one such device | |
| config USB_DWC3_MESON_G12A | |
| tristate "Amlogic Meson G12A Platforms" | |
| depends on OF && COMMON_CLK | |
| depends on ARCH_MESON || COMPILE_TEST | |
| default USB_DWC3 | |
| select USB_ROLE_SWITCH | |
| select REGMAP_MMIO | |
| help | |
| Support USB2/3 functionality in Amlogic G12A platforms. | |
| Say 'Y' or 'M' if you have one such device. | |
| config USB_DWC3_OF_SIMPLE | |
| tristate "Generic OF Simple Glue Layer" | |
| depends on OF && COMMON_CLK | |
| default USB_DWC3 | |
| help | |
| Support USB2/3 functionality in simple SoC integrations. | |
| Currently supports Xilinx and Qualcomm DWC USB3 IP. | |
| Say 'Y' or 'M' if you have one such device. | |
| config USB_DWC3_ST | |
| tristate "STMicroelectronics Platforms" | |
| depends on (ARCH_STI || COMPILE_TEST) && OF | |
| default USB_DWC3 | |
| help | |
| STMicroelectronics SoCs with one DesignWare Core USB3 IP | |
| inside (i.e. STiH407). | |
| Say 'Y' or 'M' if you have one such device. | |
| config USB_DWC3_QCOM | |
| tristate "Qualcomm Platform" | |
| depends on ARCH_QCOM || COMPILE_TEST | |
| depends on EXTCON || !EXTCON | |
| depends on OF | |
| default USB_DWC3 | |
| help | |
| Some Qualcomm SoCs use DesignWare Core IP for USB2/3 | |
| functionality. | |
| This driver also handles Qscratch wrapper which is needed | |
| for peripheral mode support. | |
| Say 'Y' or 'M' if you have one such device. | |
| config USB_DWC3_IMX8MP | |
| tristate "NXP iMX8MP Platform" | |
| depends on OF && COMMON_CLK | |
| depends on (ARCH_MXC && ARM64) || COMPILE_TEST | |
| default USB_DWC3 | |
| help | |
| NXP iMX8M Plus SoC use DesignWare Core IP for USB2/3 | |
| functionality. | |
| Say 'Y' or 'M' if you have one such device. | |
| config USB_DWC3_IMX | |
| tristate "NXP iMX Platform" | |
| depends on OF && COMMON_CLK | |
| depends on (ARCH_MXC && ARM64) || COMPILE_TEST | |
| default USB_DWC3 | |
| help | |
| NXP iMX SoC use DesignWare Core IP for USB2/3 | |
| functionality. | |
| This driver also handles the wakeup feature outside | |
| of DesignWare Core. | |
| Say 'Y' or 'M' if you have one such device. | |
| config USB_DWC3_XILINX | |
| tristate "Xilinx Platforms" | |
| depends on (ARCH_ZYNQMP || COMPILE_TEST) && OF | |
| default USB_DWC3 | |
| help | |
| Support Xilinx SoCs with DesignWare Core USB3 IP. | |
| This driver handles ZynqMP SoC operations. | |
| Say 'Y' or 'M' if you have one such device. | |
| config USB_DWC3_AM62 | |
| tristate "Texas Instruments AM62 Platforms" | |
| depends on ARCH_K3 || COMPILE_TEST | |
| default USB_DWC3 | |
| help | |
| Support TI's AM62 platforms with DesignWare Core USB3 IP. | |
| The Designware Core USB3 IP is programmed to operate in | |
| in USB 2.0 mode only. | |
| Say 'Y' or 'M' here if you have one such device | |
| config USB_DWC3_OCTEON | |
| tristate "Cavium Octeon Platforms" | |
| depends on CAVIUM_OCTEON_SOC || COMPILE_TEST | |
| default USB_DWC3 | |
| help | |
| Support Cavium Octeon platforms with DesignWare Core USB3 IP. | |
| Only the host mode is currently supported. | |
| Say 'Y' or 'M' here if you have one such device. | |
| config USB_DWC3_RTK | |
| tristate "Realtek DWC3 Platform Driver" | |
| depends on OF && ARCH_REALTEK | |
| default USB_DWC3 | |
| select USB_ROLE_SWITCH | |
| help | |
| RTK DHC RTD SoCs with DesignWare Core USB3 IP inside, | |
| and IP Core configured for USB 2.0 and USB 3.0 in host | |
| or dual-role mode. | |
| Say 'Y' or 'M' if you have such device. | |
| config USB_DWC3_GENERIC_PLAT | |
| tristate "DWC3 Generic Platform Driver" | |
| depends on OF && COMMON_CLK | |
| default USB_DWC3 | |
| help | |
| Support USB3 functionality in simple SoC integrations. | |
| Currently supports SpacemiT DWC USB3. Platforms using | |
| dwc3-of-simple can easily switch to dwc3-generic by flattening | |
| the dwc3 child node in the device tree. | |
| Say 'Y' or 'M' here if your platform integrates DWC3 in a similar way. | |
| config USB_DWC3_APPLE | |
| tristate "Apple Silicon DWC3 Platform Driver" | |
| depends on OF && ARCH_APPLE | |
| default USB_DWC3 | |
| select USB_ROLE_SWITCH | |
| help | |
| Support Apple Silicon SoCs with DesignWare Core USB3 IP. | |
| The DesignWare Core USB3 IP has to be used in dual-role | |
| mode on these machines. | |
| Say 'Y' or 'M' if you have such device. | |
| config USB_DWC3_GOOGLE | |
| tristate "Google Platform" | |
| help | |
| Support the DesignWare Core USB3 IP found on Google Tensor SoCs, | |
| starting with the G5 generation (Laguna). This driver includes | |
| support for hibernation in host mode. | |
| Say 'Y' or 'M' if you have one such device. | |
| To compile this driver as a module, choose M here: the | |
| module will be called dwc3-google.ko. | |
| endif |