| /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ |
| /* |
| * Copyright (C) 2026 Amlogic, Inc. All rights reserved. |
| */ |
| |
| #ifndef __AMLOGIC_A9_AO_CLKC_H |
| #define __AMLOGIC_A9_AO_CLKC_H |
| |
| #define CLKID_AO_XTAL_IN 0 |
| #define CLKID_AO_XTAL 1 |
| #define CLKID_AO_SYS 2 |
| #define CLKID_AO_SYS_I3C 3 |
| #define CLKID_AO_SYS_RTC_REG 4 |
| #define CLKID_AO_SYS_CLKTREE 5 |
| #define CLKID_AO_SYS_RST_CTRL 6 |
| #define CLKID_AO_SYS_PAD 7 |
| #define CLKID_AO_SYS_RTC_DIG 8 |
| #define CLKID_AO_SYS_IRQ 9 |
| #define CLKID_AO_SYS_PWRCTRL 10 |
| #define CLKID_AO_SYS_PWM_A 11 |
| #define CLKID_AO_SYS_PWM_B 12 |
| #define CLKID_AO_SYS_PWM_C 13 |
| #define CLKID_AO_SYS_PWM_D 14 |
| #define CLKID_AO_SYS_PWM_E 15 |
| #define CLKID_AO_SYS_PWM_F 16 |
| #define CLKID_AO_SYS_PWM_G 17 |
| #define CLKID_AO_SYS_I2C_A 18 |
| #define CLKID_AO_SYS_I2C_B 19 |
| #define CLKID_AO_SYS_I2C_C 20 |
| #define CLKID_AO_SYS_I2C_D 21 |
| #define CLKID_AO_SYS_SED 22 |
| #define CLKID_AO_SYS_IR_CTRL 23 |
| #define CLKID_AO_SYS_UART_B 24 |
| #define CLKID_AO_SYS_UART_C 25 |
| #define CLKID_AO_SYS_UART_D 26 |
| #define CLKID_AO_SYS_UART_E 27 |
| #define CLKID_AO_SYS_SPISG_0 28 |
| #define CLKID_AO_SYS_RTC_SECURE 29 |
| #define CLKID_AO_SYS_CEC 30 |
| #define CLKID_AO_SYS_AOCPU 31 |
| #define CLKID_AO_SYS_SRAM 32 |
| #define CLKID_AO_SYS_SPISG_1 33 |
| #define CLKID_AO_SYS_SPISG_2 34 |
| #define CLKID_AO_PWM_A_SEL 35 |
| #define CLKID_AO_PWM_A_DIV 36 |
| #define CLKID_AO_PWM_A 37 |
| #define CLKID_AO_PWM_B_SEL 38 |
| #define CLKID_AO_PWM_B_DIV 39 |
| #define CLKID_AO_PWM_B 40 |
| #define CLKID_AO_PWM_C_SEL 41 |
| #define CLKID_AO_PWM_C_DIV 42 |
| #define CLKID_AO_PWM_C 43 |
| #define CLKID_AO_PWM_D_SEL 44 |
| #define CLKID_AO_PWM_D_DIV 45 |
| #define CLKID_AO_PWM_D 46 |
| #define CLKID_AO_PWM_E_SEL 47 |
| #define CLKID_AO_PWM_E_DIV 48 |
| #define CLKID_AO_PWM_E 49 |
| #define CLKID_AO_PWM_F_SEL 50 |
| #define CLKID_AO_PWM_F_DIV 51 |
| #define CLKID_AO_PWM_F 52 |
| #define CLKID_AO_PWM_G_SEL 53 |
| #define CLKID_AO_PWM_G_DIV 54 |
| #define CLKID_AO_PWM_G 55 |
| #define CLKID_AO_RTC_DUALDIV_IN 56 |
| #define CLKID_AO_RTC_DUALDIV_DIV 57 |
| #define CLKID_AO_RTC_DUALDIV_SEL 58 |
| #define CLKID_AO_RTC_DUALDIV 59 |
| #define CLKID_AO_RTC 60 |
| #define CLKID_AO_CEC_DUALDIV_IN 61 |
| #define CLKID_AO_CEC_DUALDIV_DIV 62 |
| #define CLKID_AO_CEC_DUALDIV_SEL 63 |
| #define CLKID_AO_CEC_DUALDIV 64 |
| #define CLKID_AO_CEC 65 |
| |
| #endif /* __AMLOGIC_A9_AO_CLKC_H */ |
