| From 8a3b6629b44d3d5d07fd08c9dc20ee2b38e613e2 Mon Sep 17 00:00:00 2001 |
| From: Sasha Levin <sashal@kernel.org> |
| Date: Wed, 10 Dec 2025 10:37:58 +0800 |
| Subject: drm/hisilicon/hibmc: fix no showing problem with loading hibmc |
| manually |
| |
| From: Baihan Li <libaihan@huawei.com> |
| |
| [ Upstream commit 0607052a6aee1e3d218a99fae70ba9f14b3b47ed ] |
| |
| When using command rmmod and insmod, there is no showing in second time |
| insmoding. Because DP controller won't send HPD signals, if connection |
| doesn't change or controller isn't reset. So add reset before unreset |
| in hibmc_dp_hw_init(). |
| |
| And also need to move the HDCP cfg after DP controller de-resets, so |
| that HDCP configuration takes effect. |
| |
| Fixes: 3c7623fb5bb6 ("drm/hisilicon/hibmc: Enable this hot plug detect of irq feature") |
| Signed-off-by: Baihan Li <libaihan@huawei.com> |
| Signed-off-by: Yongbang Shi <shiyongbang@huawei.com> |
| Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> |
| Reviewed-by: Tao Tian <tiantao6@hisilicon.com> |
| Link: https://patch.msgid.link/20251210023759.3944834-4-shiyongbang@huawei.com |
| Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| --- |
| drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c | 7 +++++-- |
| 1 file changed, 5 insertions(+), 2 deletions(-) |
| |
| diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c |
| index 37549dafa06ca..8f8ca940b6b26 100644 |
| --- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c |
| +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c |
| @@ -177,13 +177,16 @@ int hibmc_dp_hw_init(struct hibmc_dp *dp) |
| dp_dev->link.cap.lanes = 0x2; |
| dp_dev->link.cap.link_rate = DP_LINK_BW_8_1; |
| |
| - /* hdcp data */ |
| - writel(HIBMC_DP_HDCP, dp_dev->base + HIBMC_DP_HDCP_CFG); |
| /* int init */ |
| writel(0, dp_dev->base + HIBMC_DP_INTR_ENABLE); |
| writel(HIBMC_DP_INT_RST, dp_dev->base + HIBMC_DP_INTR_ORIGINAL_STATUS); |
| /* rst */ |
| + writel(0, dp_dev->base + HIBMC_DP_DPTX_RST_CTRL); |
| + usleep_range(30, 50); |
| + /* de-rst */ |
| writel(HIBMC_DP_DPTX_RST, dp_dev->base + HIBMC_DP_DPTX_RST_CTRL); |
| + /* hdcp data */ |
| + writel(HIBMC_DP_HDCP, dp_dev->base + HIBMC_DP_HDCP_CFG); |
| /* clock enable */ |
| writel(HIBMC_DP_CLK_EN, dp_dev->base + HIBMC_DP_DPTX_CLK_CTRL); |
| |
| -- |
| 2.51.0 |
| |