| From 35dd0a75d4a382e7f769dd0277732e7aa5235718 Mon Sep 17 00:00:00 2001 |
| From: Roland Stigge <stigge@antcom.de> |
| Date: Mon, 27 Feb 2012 17:28:02 +0100 |
| Subject: ARM: LPC32xx: Fix interrupt controller init |
| |
| From: Roland Stigge <stigge@antcom.de> |
| |
| commit 35dd0a75d4a382e7f769dd0277732e7aa5235718 upstream. |
| |
| This patch fixes the initialization of the interrupt controller of the LPC32xx |
| by correctly setting up SIC1 and SIC2 instead of (wrongly) using the same value |
| as for the Main Interrupt Controller (MIC). |
| |
| Signed-off-by: Roland Stigge <stigge@antcom.de> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| arch/arm/mach-lpc32xx/irq.c | 10 ++++++---- |
| 1 file changed, 6 insertions(+), 4 deletions(-) |
| |
| --- a/arch/arm/mach-lpc32xx/irq.c |
| +++ b/arch/arm/mach-lpc32xx/irq.c |
| @@ -389,13 +389,15 @@ void __init lpc32xx_init_irq(void) |
| |
| /* Setup SIC1 */ |
| __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC1_BASE)); |
| - __raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC1_BASE)); |
| - __raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC1_BASE)); |
| + __raw_writel(SIC1_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC1_BASE)); |
| + __raw_writel(SIC1_ATR_DEFAULT, |
| + LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC1_BASE)); |
| |
| /* Setup SIC2 */ |
| __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE)); |
| - __raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC2_BASE)); |
| - __raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC2_BASE)); |
| + __raw_writel(SIC2_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC2_BASE)); |
| + __raw_writel(SIC2_ATR_DEFAULT, |
| + LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC2_BASE)); |
| |
| /* Configure supported IRQ's */ |
| for (i = 0; i < NR_IRQS; i++) { |
