| From 925fe08bce38d1ff052fe2209b9e2b8d5fbb7f98 Mon Sep 17 00:00:00 2001 |
| From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> |
| Date: Wed, 27 Mar 2013 18:51:52 -0500 |
| Subject: iommu/amd: Re-enable IOMMU event log interrupt after handling. |
| |
| From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> |
| |
| commit 925fe08bce38d1ff052fe2209b9e2b8d5fbb7f98 upstream. |
| |
| Current driver does not clear the IOMMU event log interrupt bit |
| in the IOMMU status register after processing an interrupt. |
| This causes the IOMMU hardware to generate event log interrupt only once. |
| This has been observed in both IOMMU v1 and V2 hardware. |
| This patch clears the bit by writing 1 to bit 1 of the IOMMU |
| status register (MMIO Offset 2020h) |
| |
| Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> |
| Signed-off-by: Joerg Roedel <joro@8bytes.org> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| drivers/iommu/amd_iommu.c | 3 +++ |
| drivers/iommu/amd_iommu_types.h | 1 + |
| 2 files changed, 4 insertions(+) |
| |
| --- a/drivers/iommu/amd_iommu.c |
| +++ b/drivers/iommu/amd_iommu.c |
| @@ -534,6 +534,9 @@ static void iommu_poll_events(struct amd |
| u32 head, tail; |
| unsigned long flags; |
| |
| + /* enable event interrupts again */ |
| + writel(MMIO_STATUS_EVT_INT_MASK, iommu->mmio_base + MMIO_STATUS_OFFSET); |
| + |
| spin_lock_irqsave(&iommu->lock, flags); |
| |
| head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); |
| --- a/drivers/iommu/amd_iommu_types.h |
| +++ b/drivers/iommu/amd_iommu_types.h |
| @@ -99,6 +99,7 @@ |
| #define PASID_MASK 0x000fffff |
| |
| /* MMIO status bits */ |
| +#define MMIO_STATUS_EVT_INT_MASK (1 << 1) |
| #define MMIO_STATUS_COM_WAIT_INT_MASK (1 << 2) |
| #define MMIO_STATUS_PPR_INT_MASK (1 << 6) |
| |
