| From 7c1c7c18fc752b2a1d07597286467ef186312463 Mon Sep 17 00:00:00 2001 |
| From: Alex Deucher <alexander.deucher@amd.com> |
| Date: Fri, 5 Apr 2013 10:28:08 -0400 |
| Subject: drm/radeon/dce6: add missing display reg for tiling setup |
| |
| From: Alex Deucher <alexander.deucher@amd.com> |
| |
| commit 7c1c7c18fc752b2a1d07597286467ef186312463 upstream. |
| |
| A new tiling config register for the display blocks was |
| added on DCE6. |
| |
| May fix: |
| https://bugs.freedesktop.org/show_bug.cgi?id=62889 |
| https://bugs.freedesktop.org/show_bug.cgi?id=57919 |
| |
| Signed-off-by: Alex Deucher <alexander.deucher@amd.com> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| drivers/gpu/drm/radeon/ni.c | 2 ++ |
| drivers/gpu/drm/radeon/nid.h | 4 ++++ |
| drivers/gpu/drm/radeon/si.c | 1 + |
| drivers/gpu/drm/radeon/sid.h | 2 ++ |
| 4 files changed, 9 insertions(+) |
| |
| --- a/drivers/gpu/drm/radeon/ni.c |
| +++ b/drivers/gpu/drm/radeon/ni.c |
| @@ -621,6 +621,8 @@ static void cayman_gpu_init(struct radeo |
| |
| WREG32(GB_ADDR_CONFIG, gb_addr_config); |
| WREG32(DMIF_ADDR_CONFIG, gb_addr_config); |
| + if (ASIC_IS_DCE6(rdev)) |
| + WREG32(DMIF_ADDR_CALC, gb_addr_config); |
| WREG32(HDP_ADDR_CONFIG, gb_addr_config); |
| WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); |
| WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); |
| --- a/drivers/gpu/drm/radeon/nid.h |
| +++ b/drivers/gpu/drm/radeon/nid.h |
| @@ -45,6 +45,10 @@ |
| #define ARUBA_GB_ADDR_CONFIG_GOLDEN 0x12010001 |
| |
| #define DMIF_ADDR_CONFIG 0xBD4 |
| + |
| +/* DCE6 only */ |
| +#define DMIF_ADDR_CALC 0xC00 |
| + |
| #define SRBM_GFX_CNTL 0x0E44 |
| #define RINGID(x) (((x) & 0x3) << 0) |
| #define VMID(x) (((x) & 0x7) << 0) |
| --- a/drivers/gpu/drm/radeon/si.c |
| +++ b/drivers/gpu/drm/radeon/si.c |
| @@ -1765,6 +1765,7 @@ static void si_gpu_init(struct radeon_de |
| |
| WREG32(GB_ADDR_CONFIG, gb_addr_config); |
| WREG32(DMIF_ADDR_CONFIG, gb_addr_config); |
| + WREG32(DMIF_ADDR_CALC, gb_addr_config); |
| WREG32(HDP_ADDR_CONFIG, gb_addr_config); |
| WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); |
| WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); |
| --- a/drivers/gpu/drm/radeon/sid.h |
| +++ b/drivers/gpu/drm/radeon/sid.h |
| @@ -65,6 +65,8 @@ |
| |
| #define DMIF_ADDR_CONFIG 0xBD4 |
| |
| +#define DMIF_ADDR_CALC 0xC00 |
| + |
| #define SRBM_STATUS 0xE50 |
| #define GRBM_RQ_PENDING (1 << 5) |
| #define VMC_BUSY (1 << 8) |