| From 396f5d62d1a5fd99421855a08ffdef8edb43c76e Mon Sep 17 00:00:00 2001 | 
 | From: Chris Wilson <chris@chris-wilson.co.uk> | 
 | Date: Thu, 7 Jul 2016 09:41:12 +0100 | 
 | Subject: drm: Restore double clflush on the last partial cacheline | 
 |  | 
 | From: Chris Wilson <chris@chris-wilson.co.uk> | 
 |  | 
 | commit 396f5d62d1a5fd99421855a08ffdef8edb43c76e upstream. | 
 |  | 
 | This effectively reverts | 
 |  | 
 | commit afcd950cafea6e27b739fe7772cbbeed37d05b8b | 
 | Author: Chris Wilson <chris@chris-wilson.co.uk> | 
 | Date:   Wed Jun 10 15:58:01 2015 +0100 | 
 |  | 
 |     drm: Avoid the double clflush on the last cache line in drm_clflush_virt_range() | 
 |  | 
 | as we have observed issues with serialisation of the clflush operations | 
 | on Baytrail+ Atoms with partial updates. Applying the double flush on the | 
 | last cacheline forces that clflush to be ordered with respect to the | 
 | previous clflush, and the mfence then protects against prefetches crossing | 
 | the clflush boundary. | 
 |  | 
 | The same issue can be demonstrated in userspace with igt/gem_exec_flush. | 
 |  | 
 | Fixes: afcd950cafea6 (drm: Avoid the double clflush on the last cache...) | 
 | Testcase: igt/gem_concurrent_blit | 
 | Testcase: igt/gem_partial_pread_pwrite | 
 | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92845 | 
 | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> | 
 | Cc: dri-devel@lists.freedesktop.org | 
 | Cc: Akash Goel <akash.goel@intel.com> | 
 | Cc: Imre Deak <imre.deak@intel.com> | 
 | Cc: Daniel Vetter <daniel.vetter@ffwll.ch> | 
 | Cc: Jason Ekstrand <jason.ekstrand@intel.com> | 
 | Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> | 
 | Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> | 
 | Link: http://patchwork.freedesktop.org/patch/msgid/1467880930-23082-6-git-send-email-chris@chris-wilson.co.uk | 
 | Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 
 |  | 
 | --- | 
 |  drivers/gpu/drm/drm_cache.c |    1 + | 
 |  1 file changed, 1 insertion(+) | 
 |  | 
 | --- a/drivers/gpu/drm/drm_cache.c | 
 | +++ b/drivers/gpu/drm/drm_cache.c | 
 | @@ -136,6 +136,7 @@ drm_clflush_virt_range(void *addr, unsig | 
 |  		mb(); | 
 |  		for (; addr < end; addr += size) | 
 |  			clflushopt(addr); | 
 | +		clflushopt(end - 1); /* force serialisation */ | 
 |  		mb(); | 
 |  		return; | 
 |  	} |