| From 4f53989b0652ffe2605221c81ca8ffcfc90aed2a Mon Sep 17 00:00:00 2001 |
| From: Matt Redfearn <matt.redfearn@imgtec.com> |
| Date: Tue, 14 Jun 2016 14:59:38 +0100 |
| Subject: MIPS: mm: Fix definition of R6 cache instruction |
| |
| From: Matt Redfearn <matt.redfearn@imgtec.com> |
| |
| commit 4f53989b0652ffe2605221c81ca8ffcfc90aed2a upstream. |
| |
| Commit a168b8f1cde6 ("MIPS: mm: Add MIPS R6 instruction encodings") added |
| an incorrect definition of the redefined MIPSr6 cache instruction. |
| |
| Executing any kernel code including this instuction results in a |
| reserved instruction exception and kernel panic. |
| |
| Fix the instruction definition. |
| |
| Fixes: a168b8f1cde6588ff7a67699fa11e01bc77a5ddd |
| Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> |
| Cc: linux-mips@linux-mips.org |
| Cc: linux-kernel@vger.kernel.org |
| Patchwork: https://patchwork.linux-mips.org/patch/13663/ |
| Signed-off-by: Ralf Baechle <ralf@linux-mips.org> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| arch/mips/mm/uasm-mips.c | 2 +- |
| 1 file changed, 1 insertion(+), 1 deletion(-) |
| |
| --- a/arch/mips/mm/uasm-mips.c |
| +++ b/arch/mips/mm/uasm-mips.c |
| @@ -65,7 +65,7 @@ static struct insn insn_table[] = { |
| #ifndef CONFIG_CPU_MIPSR6 |
| { insn_cache, M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, |
| #else |
| - { insn_cache, M6(cache_op, 0, 0, 0, cache6_op), RS | RT | SIMM9 }, |
| + { insn_cache, M6(spec3_op, 0, 0, 0, cache6_op), RS | RT | SIMM9 }, |
| #endif |
| { insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, |
| { insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD }, |
