| From 4e6ce4dc7ce71d0886908d55129d5d6482a27ff9 Mon Sep 17 00:00:00 2001 |
| From: Miaoqing Pan <miaoqing@qca.qualcomm.com> |
| Date: Thu, 6 Nov 2014 10:52:23 +0530 |
| Subject: ath9k: Fix RTC_DERIVED_CLK usage |
| |
| From: Miaoqing Pan <miaoqing@qca.qualcomm.com> |
| |
| commit 4e6ce4dc7ce71d0886908d55129d5d6482a27ff9 upstream. |
| |
| Based on the reference clock, which could be 25MHz or 40MHz, |
| AR_RTC_DERIVED_CLK is programmed differently for AR9340 and AR9550. |
| But, when a chip reset is done, processing the initvals |
| sets the register back to the default value. |
| |
| Fix this by moving the code in ath9k_hw_init_pll() to |
| ar9003_hw_override_ini(). Also, do this override for AR9531. |
| |
| Signed-off-by: Miaoqing Pan <miaoqing@qca.qualcomm.com> |
| Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com> |
| Signed-off-by: John W. Linville <linville@tuxdriver.com> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| drivers/net/wireless/ath/ath9k/ar9003_phy.c | 13 +++++++++++++ |
| drivers/net/wireless/ath/ath9k/hw.c | 13 ------------- |
| 2 files changed, 13 insertions(+), 13 deletions(-) |
| |
| --- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c |
| +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c |
| @@ -647,6 +647,19 @@ static void ar9003_hw_override_ini(struc |
| ah->enabled_cals |= TX_CL_CAL; |
| else |
| ah->enabled_cals &= ~TX_CL_CAL; |
| + |
| + if (AR_SREV_9340(ah) || AR_SREV_9531(ah) || AR_SREV_9550(ah)) { |
| + if (ah->is_clk_25mhz) { |
| + REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1); |
| + REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7); |
| + REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae); |
| + } else { |
| + REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1); |
| + REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400); |
| + REG_WRITE(ah, AR_SLP32_INC, 0x0001e800); |
| + } |
| + udelay(100); |
| + } |
| } |
| |
| static void ar9003_hw_prog_ini(struct ath_hw *ah, |
| --- a/drivers/net/wireless/ath/ath9k/hw.c |
| +++ b/drivers/net/wireless/ath/ath9k/hw.c |
| @@ -858,19 +858,6 @@ static void ath9k_hw_init_pll(struct ath |
| udelay(RTC_PLL_SETTLE_DELAY); |
| |
| REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); |
| - |
| - if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) { |
| - if (ah->is_clk_25mhz) { |
| - REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1); |
| - REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7); |
| - REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae); |
| - } else { |
| - REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1); |
| - REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400); |
| - REG_WRITE(ah, AR_SLP32_INC, 0x0001e800); |
| - } |
| - udelay(100); |
| - } |
| } |
| |
| static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, |