| From 34027ca2bbc6043fea8fc5c4a82670518b6be7df Mon Sep 17 00:00:00 2001 |
| From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de> |
| Date: Wed, 28 Jan 2015 00:45:56 +0100 |
| Subject: pinctrl: imx25: fix numbering for pins |
| MIME-Version: 1.0 |
| Content-Type: text/plain; charset=UTF-8 |
| Content-Transfer-Encoding: 8bit |
| |
| From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de> |
| |
| commit 34027ca2bbc6043fea8fc5c4a82670518b6be7df upstream. |
| |
| The pin id for a given tuple listed in a fsl,pins property is calculated |
| by dividing the first entry (which is also a register offset) by 4. |
| As the first available register is at offset 0x8 and configures the pad |
| MX25_PAD_A10 the right id for this pin is 2. All other pins are off by |
| one, too. |
| |
| This patch drops the definition MX25_PAD_RESERVE1 (together with its |
| only use) and decrements all following values by 1. |
| |
| Fixes: b4a87c9b966f ("pinctrl: pinctrl-imx: add imx25 pinctrl driver") |
| Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> |
| Tested-by: Fabio Estevam <fabio.estevam@freescale.com> |
| Signed-off-by: Linus Walleij <linus.walleij@linaro.org> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| drivers/pinctrl/freescale/pinctrl-imx25.c | 276 ++++++++++++++---------------- |
| 1 file changed, 137 insertions(+), 139 deletions(-) |
| |
| --- a/drivers/pinctrl/freescale/pinctrl-imx25.c |
| +++ b/drivers/pinctrl/freescale/pinctrl-imx25.c |
| @@ -27,150 +27,148 @@ |
| |
| enum imx25_pads { |
| MX25_PAD_RESERVE0 = 1, |
| - MX25_PAD_RESERVE1 = 2, |
| - MX25_PAD_A10 = 3, |
| - MX25_PAD_A13 = 4, |
| - MX25_PAD_A14 = 5, |
| - MX25_PAD_A15 = 6, |
| - MX25_PAD_A16 = 7, |
| - MX25_PAD_A17 = 8, |
| - MX25_PAD_A18 = 9, |
| - MX25_PAD_A19 = 10, |
| - MX25_PAD_A20 = 11, |
| - MX25_PAD_A21 = 12, |
| - MX25_PAD_A22 = 13, |
| - MX25_PAD_A23 = 14, |
| - MX25_PAD_A24 = 15, |
| - MX25_PAD_A25 = 16, |
| - MX25_PAD_EB0 = 17, |
| - MX25_PAD_EB1 = 18, |
| - MX25_PAD_OE = 19, |
| - MX25_PAD_CS0 = 20, |
| - MX25_PAD_CS1 = 21, |
| - MX25_PAD_CS4 = 22, |
| - MX25_PAD_CS5 = 23, |
| - MX25_PAD_NF_CE0 = 24, |
| - MX25_PAD_ECB = 25, |
| - MX25_PAD_LBA = 26, |
| - MX25_PAD_BCLK = 27, |
| - MX25_PAD_RW = 28, |
| - MX25_PAD_NFWE_B = 29, |
| - MX25_PAD_NFRE_B = 30, |
| - MX25_PAD_NFALE = 31, |
| - MX25_PAD_NFCLE = 32, |
| - MX25_PAD_NFWP_B = 33, |
| - MX25_PAD_NFRB = 34, |
| - MX25_PAD_D15 = 35, |
| - MX25_PAD_D14 = 36, |
| - MX25_PAD_D13 = 37, |
| - MX25_PAD_D12 = 38, |
| - MX25_PAD_D11 = 39, |
| - MX25_PAD_D10 = 40, |
| - MX25_PAD_D9 = 41, |
| - MX25_PAD_D8 = 42, |
| - MX25_PAD_D7 = 43, |
| - MX25_PAD_D6 = 44, |
| - MX25_PAD_D5 = 45, |
| - MX25_PAD_D4 = 46, |
| - MX25_PAD_D3 = 47, |
| - MX25_PAD_D2 = 48, |
| - MX25_PAD_D1 = 49, |
| - MX25_PAD_D0 = 50, |
| - MX25_PAD_LD0 = 51, |
| - MX25_PAD_LD1 = 52, |
| - MX25_PAD_LD2 = 53, |
| - MX25_PAD_LD3 = 54, |
| - MX25_PAD_LD4 = 55, |
| - MX25_PAD_LD5 = 56, |
| - MX25_PAD_LD6 = 57, |
| - MX25_PAD_LD7 = 58, |
| - MX25_PAD_LD8 = 59, |
| - MX25_PAD_LD9 = 60, |
| - MX25_PAD_LD10 = 61, |
| - MX25_PAD_LD11 = 62, |
| - MX25_PAD_LD12 = 63, |
| - MX25_PAD_LD13 = 64, |
| - MX25_PAD_LD14 = 65, |
| - MX25_PAD_LD15 = 66, |
| - MX25_PAD_HSYNC = 67, |
| - MX25_PAD_VSYNC = 68, |
| - MX25_PAD_LSCLK = 69, |
| - MX25_PAD_OE_ACD = 70, |
| - MX25_PAD_CONTRAST = 71, |
| - MX25_PAD_PWM = 72, |
| - MX25_PAD_CSI_D2 = 73, |
| - MX25_PAD_CSI_D3 = 74, |
| - MX25_PAD_CSI_D4 = 75, |
| - MX25_PAD_CSI_D5 = 76, |
| - MX25_PAD_CSI_D6 = 77, |
| - MX25_PAD_CSI_D7 = 78, |
| - MX25_PAD_CSI_D8 = 79, |
| - MX25_PAD_CSI_D9 = 80, |
| - MX25_PAD_CSI_MCLK = 81, |
| - MX25_PAD_CSI_VSYNC = 82, |
| - MX25_PAD_CSI_HSYNC = 83, |
| - MX25_PAD_CSI_PIXCLK = 84, |
| - MX25_PAD_I2C1_CLK = 85, |
| - MX25_PAD_I2C1_DAT = 86, |
| - MX25_PAD_CSPI1_MOSI = 87, |
| - MX25_PAD_CSPI1_MISO = 88, |
| - MX25_PAD_CSPI1_SS0 = 89, |
| - MX25_PAD_CSPI1_SS1 = 90, |
| - MX25_PAD_CSPI1_SCLK = 91, |
| - MX25_PAD_CSPI1_RDY = 92, |
| - MX25_PAD_UART1_RXD = 93, |
| - MX25_PAD_UART1_TXD = 94, |
| - MX25_PAD_UART1_RTS = 95, |
| - MX25_PAD_UART1_CTS = 96, |
| - MX25_PAD_UART2_RXD = 97, |
| - MX25_PAD_UART2_TXD = 98, |
| - MX25_PAD_UART2_RTS = 99, |
| - MX25_PAD_UART2_CTS = 100, |
| - MX25_PAD_SD1_CMD = 101, |
| - MX25_PAD_SD1_CLK = 102, |
| - MX25_PAD_SD1_DATA0 = 103, |
| - MX25_PAD_SD1_DATA1 = 104, |
| - MX25_PAD_SD1_DATA2 = 105, |
| - MX25_PAD_SD1_DATA3 = 106, |
| - MX25_PAD_KPP_ROW0 = 107, |
| - MX25_PAD_KPP_ROW1 = 108, |
| - MX25_PAD_KPP_ROW2 = 109, |
| - MX25_PAD_KPP_ROW3 = 110, |
| - MX25_PAD_KPP_COL0 = 111, |
| - MX25_PAD_KPP_COL1 = 112, |
| - MX25_PAD_KPP_COL2 = 113, |
| - MX25_PAD_KPP_COL3 = 114, |
| - MX25_PAD_FEC_MDC = 115, |
| - MX25_PAD_FEC_MDIO = 116, |
| - MX25_PAD_FEC_TDATA0 = 117, |
| - MX25_PAD_FEC_TDATA1 = 118, |
| - MX25_PAD_FEC_TX_EN = 119, |
| - MX25_PAD_FEC_RDATA0 = 120, |
| - MX25_PAD_FEC_RDATA1 = 121, |
| - MX25_PAD_FEC_RX_DV = 122, |
| - MX25_PAD_FEC_TX_CLK = 123, |
| - MX25_PAD_RTCK = 124, |
| - MX25_PAD_DE_B = 125, |
| - MX25_PAD_GPIO_A = 126, |
| - MX25_PAD_GPIO_B = 127, |
| - MX25_PAD_GPIO_C = 128, |
| - MX25_PAD_GPIO_D = 129, |
| - MX25_PAD_GPIO_E = 130, |
| - MX25_PAD_GPIO_F = 131, |
| - MX25_PAD_EXT_ARMCLK = 132, |
| - MX25_PAD_UPLL_BYPCLK = 133, |
| - MX25_PAD_VSTBY_REQ = 134, |
| - MX25_PAD_VSTBY_ACK = 135, |
| - MX25_PAD_POWER_FAIL = 136, |
| - MX25_PAD_CLKO = 137, |
| - MX25_PAD_BOOT_MODE0 = 138, |
| - MX25_PAD_BOOT_MODE1 = 139, |
| + MX25_PAD_A10 = 2, |
| + MX25_PAD_A13 = 3, |
| + MX25_PAD_A14 = 4, |
| + MX25_PAD_A15 = 5, |
| + MX25_PAD_A16 = 6, |
| + MX25_PAD_A17 = 7, |
| + MX25_PAD_A18 = 8, |
| + MX25_PAD_A19 = 9, |
| + MX25_PAD_A20 = 10, |
| + MX25_PAD_A21 = 11, |
| + MX25_PAD_A22 = 12, |
| + MX25_PAD_A23 = 13, |
| + MX25_PAD_A24 = 14, |
| + MX25_PAD_A25 = 15, |
| + MX25_PAD_EB0 = 16, |
| + MX25_PAD_EB1 = 17, |
| + MX25_PAD_OE = 18, |
| + MX25_PAD_CS0 = 19, |
| + MX25_PAD_CS1 = 20, |
| + MX25_PAD_CS4 = 21, |
| + MX25_PAD_CS5 = 22, |
| + MX25_PAD_NF_CE0 = 23, |
| + MX25_PAD_ECB = 24, |
| + MX25_PAD_LBA = 25, |
| + MX25_PAD_BCLK = 26, |
| + MX25_PAD_RW = 27, |
| + MX25_PAD_NFWE_B = 28, |
| + MX25_PAD_NFRE_B = 29, |
| + MX25_PAD_NFALE = 30, |
| + MX25_PAD_NFCLE = 31, |
| + MX25_PAD_NFWP_B = 32, |
| + MX25_PAD_NFRB = 33, |
| + MX25_PAD_D15 = 34, |
| + MX25_PAD_D14 = 35, |
| + MX25_PAD_D13 = 36, |
| + MX25_PAD_D12 = 37, |
| + MX25_PAD_D11 = 38, |
| + MX25_PAD_D10 = 39, |
| + MX25_PAD_D9 = 40, |
| + MX25_PAD_D8 = 41, |
| + MX25_PAD_D7 = 42, |
| + MX25_PAD_D6 = 43, |
| + MX25_PAD_D5 = 44, |
| + MX25_PAD_D4 = 45, |
| + MX25_PAD_D3 = 46, |
| + MX25_PAD_D2 = 47, |
| + MX25_PAD_D1 = 48, |
| + MX25_PAD_D0 = 49, |
| + MX25_PAD_LD0 = 50, |
| + MX25_PAD_LD1 = 51, |
| + MX25_PAD_LD2 = 52, |
| + MX25_PAD_LD3 = 53, |
| + MX25_PAD_LD4 = 54, |
| + MX25_PAD_LD5 = 55, |
| + MX25_PAD_LD6 = 56, |
| + MX25_PAD_LD7 = 57, |
| + MX25_PAD_LD8 = 58, |
| + MX25_PAD_LD9 = 59, |
| + MX25_PAD_LD10 = 60, |
| + MX25_PAD_LD11 = 61, |
| + MX25_PAD_LD12 = 62, |
| + MX25_PAD_LD13 = 63, |
| + MX25_PAD_LD14 = 64, |
| + MX25_PAD_LD15 = 65, |
| + MX25_PAD_HSYNC = 66, |
| + MX25_PAD_VSYNC = 67, |
| + MX25_PAD_LSCLK = 68, |
| + MX25_PAD_OE_ACD = 69, |
| + MX25_PAD_CONTRAST = 70, |
| + MX25_PAD_PWM = 71, |
| + MX25_PAD_CSI_D2 = 72, |
| + MX25_PAD_CSI_D3 = 73, |
| + MX25_PAD_CSI_D4 = 74, |
| + MX25_PAD_CSI_D5 = 75, |
| + MX25_PAD_CSI_D6 = 76, |
| + MX25_PAD_CSI_D7 = 77, |
| + MX25_PAD_CSI_D8 = 78, |
| + MX25_PAD_CSI_D9 = 79, |
| + MX25_PAD_CSI_MCLK = 80, |
| + MX25_PAD_CSI_VSYNC = 81, |
| + MX25_PAD_CSI_HSYNC = 82, |
| + MX25_PAD_CSI_PIXCLK = 83, |
| + MX25_PAD_I2C1_CLK = 84, |
| + MX25_PAD_I2C1_DAT = 85, |
| + MX25_PAD_CSPI1_MOSI = 86, |
| + MX25_PAD_CSPI1_MISO = 87, |
| + MX25_PAD_CSPI1_SS0 = 88, |
| + MX25_PAD_CSPI1_SS1 = 89, |
| + MX25_PAD_CSPI1_SCLK = 90, |
| + MX25_PAD_CSPI1_RDY = 91, |
| + MX25_PAD_UART1_RXD = 92, |
| + MX25_PAD_UART1_TXD = 93, |
| + MX25_PAD_UART1_RTS = 94, |
| + MX25_PAD_UART1_CTS = 95, |
| + MX25_PAD_UART2_RXD = 96, |
| + MX25_PAD_UART2_TXD = 97, |
| + MX25_PAD_UART2_RTS = 98, |
| + MX25_PAD_UART2_CTS = 99, |
| + MX25_PAD_SD1_CMD = 100, |
| + MX25_PAD_SD1_CLK = 101, |
| + MX25_PAD_SD1_DATA0 = 102, |
| + MX25_PAD_SD1_DATA1 = 103, |
| + MX25_PAD_SD1_DATA2 = 104, |
| + MX25_PAD_SD1_DATA3 = 105, |
| + MX25_PAD_KPP_ROW0 = 106, |
| + MX25_PAD_KPP_ROW1 = 107, |
| + MX25_PAD_KPP_ROW2 = 108, |
| + MX25_PAD_KPP_ROW3 = 109, |
| + MX25_PAD_KPP_COL0 = 110, |
| + MX25_PAD_KPP_COL1 = 111, |
| + MX25_PAD_KPP_COL2 = 112, |
| + MX25_PAD_KPP_COL3 = 113, |
| + MX25_PAD_FEC_MDC = 114, |
| + MX25_PAD_FEC_MDIO = 115, |
| + MX25_PAD_FEC_TDATA0 = 116, |
| + MX25_PAD_FEC_TDATA1 = 117, |
| + MX25_PAD_FEC_TX_EN = 118, |
| + MX25_PAD_FEC_RDATA0 = 119, |
| + MX25_PAD_FEC_RDATA1 = 120, |
| + MX25_PAD_FEC_RX_DV = 121, |
| + MX25_PAD_FEC_TX_CLK = 122, |
| + MX25_PAD_RTCK = 123, |
| + MX25_PAD_DE_B = 124, |
| + MX25_PAD_GPIO_A = 125, |
| + MX25_PAD_GPIO_B = 126, |
| + MX25_PAD_GPIO_C = 127, |
| + MX25_PAD_GPIO_D = 128, |
| + MX25_PAD_GPIO_E = 129, |
| + MX25_PAD_GPIO_F = 130, |
| + MX25_PAD_EXT_ARMCLK = 131, |
| + MX25_PAD_UPLL_BYPCLK = 132, |
| + MX25_PAD_VSTBY_REQ = 133, |
| + MX25_PAD_VSTBY_ACK = 134, |
| + MX25_PAD_POWER_FAIL = 135, |
| + MX25_PAD_CLKO = 136, |
| + MX25_PAD_BOOT_MODE0 = 137, |
| + MX25_PAD_BOOT_MODE1 = 138, |
| }; |
| |
| /* Pad names for the pinmux subsystem */ |
| static const struct pinctrl_pin_desc imx25_pinctrl_pads[] = { |
| IMX_PINCTRL_PIN(MX25_PAD_RESERVE0), |
| - IMX_PINCTRL_PIN(MX25_PAD_RESERVE1), |
| IMX_PINCTRL_PIN(MX25_PAD_A10), |
| IMX_PINCTRL_PIN(MX25_PAD_A13), |
| IMX_PINCTRL_PIN(MX25_PAD_A14), |