| From 827c50b9f40faec7daf548d8f31d745ce3dcaf93 Mon Sep 17 00:00:00 2001 |
| From: shaoyunl <shaoyun.liu@amd.com> |
| Date: Thu, 22 Nov 2018 11:45:24 -0500 |
| Subject: drm/amdgpu: Add delay after enable RLC ucode |
| |
| [ Upstream commit ad97d9de45835b6a0f71983b0ae0cffd7306730a ] |
| |
| Driver shouldn't try to access any GFX registers until RLC is idle. |
| During the test, it took 12 seconds for RLC to clear the BUSY bit |
| in RLC_GPM_STAT register which is un-acceptable for driver. |
| As per RLC engineer, it would take RLC Ucode less than 10,000 GFXCLK |
| cycles to finish its critical section. In a lowest 300M enginer clock |
| setting(default from vbios), 50 us delay is enough. |
| |
| This commit fix the hang when RLC introduce the work around for XGMI |
| which requires more cycles to setup more registers than normal |
| |
| Signed-off-by: shaoyunl <shaoyun.liu@amd.com> |
| Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> |
| Signed-off-by: Alex Deucher <alexander.deucher@amd.com> |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| --- |
| drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 7 ++++--- |
| 1 file changed, 4 insertions(+), 3 deletions(-) |
| |
| diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c |
| index ef00d14f8645..325e2213cac5 100644 |
| --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c |
| +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c |
| @@ -2243,12 +2243,13 @@ static void gfx_v9_0_rlc_start(struct amdgpu_device *adev) |
| #endif |
| |
| WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); |
| + udelay(50); |
| |
| /* carrizo do enable cp interrupt after cp inited */ |
| - if (!(adev->flags & AMD_IS_APU)) |
| + if (!(adev->flags & AMD_IS_APU)) { |
| gfx_v9_0_enable_gui_idle_interrupt(adev, true); |
| - |
| - udelay(50); |
| + udelay(50); |
| + } |
| |
| #ifdef AMDGPU_RLC_DEBUG_RETRY |
| /* RLC_GPM_GENERAL_6 : RLC Ucode version */ |
| -- |
| 2.19.1 |
| |
