| From 8a17f372a218576c6e3613cbfbc5d5f65c120554 Mon Sep 17 00:00:00 2001 |
| From: Daniel Mack <daniel@zonque.org> |
| Date: Wed, 20 Mar 2019 22:41:56 +0100 |
| Subject: ASoC: cs4270: Set auto-increment bit for register writes |
| |
| [ Upstream commit f0f2338a9cfaf71db895fa989ea7234e8a9b471d ] |
| |
| The CS4270 does not by default increment the register address on |
| consecutive writes. During normal operation it doesn't matter as all |
| register accesses are done individually. At resume time after suspend, |
| however, the regcache code gathers the biggest possible block of |
| registers to sync and sends them one on one go. |
| |
| To fix this, set the INCR bit in all cases. |
| |
| Signed-off-by: Daniel Mack <daniel@zonque.org> |
| Signed-off-by: Mark Brown <broonie@kernel.org> |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| --- |
| sound/soc/codecs/cs4270.c | 1 + |
| 1 file changed, 1 insertion(+) |
| |
| diff --git a/sound/soc/codecs/cs4270.c b/sound/soc/codecs/cs4270.c |
| index 3c266eeb89bfb..007ce9f48e443 100644 |
| --- a/sound/soc/codecs/cs4270.c |
| +++ b/sound/soc/codecs/cs4270.c |
| @@ -642,6 +642,7 @@ static const struct regmap_config cs4270_regmap = { |
| .reg_defaults = cs4270_reg_defaults, |
| .num_reg_defaults = ARRAY_SIZE(cs4270_reg_defaults), |
| .cache_type = REGCACHE_RBTREE, |
| + .write_flag_mask = CS4270_I2C_INCR, |
| |
| .readable_reg = cs4270_reg_is_readable, |
| .volatile_reg = cs4270_reg_is_volatile, |
| -- |
| 2.20.1 |
| |
