| From foo@baz Thu May 24 11:23:00 CEST 2018 |
| From: Thinh Nguyen <Thinh.Nguyen@synopsys.com> |
| Date: Fri, 16 Mar 2018 15:33:48 -0700 |
| Subject: usb: dwc3: Add SoftReset PHY synchonization delay |
| |
| From: Thinh Nguyen <Thinh.Nguyen@synopsys.com> |
| |
| [ Upstream commit fab3833338779e1e668bd58d1f76d601657304b8 ] |
| |
| >From DWC_usb31 programming guide section 1.3.2, once DWC3_DCTL_CSFTRST |
| bit is cleared, we must wait at least 50ms before accessing the PHY |
| domain (synchronization delay). |
| |
| Signed-off-by: Thinh Nguyen <thinhn@synopsys.com> |
| Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> |
| Signed-off-by: Sasha Levin <alexander.levin@microsoft.com> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| --- |
| drivers/usb/dwc3/core.c | 13 ++++++++++++- |
| 1 file changed, 12 insertions(+), 1 deletion(-) |
| |
| --- a/drivers/usb/dwc3/core.c |
| +++ b/drivers/usb/dwc3/core.c |
| @@ -161,7 +161,7 @@ static int dwc3_core_soft_reset(struct d |
| do { |
| reg = dwc3_readl(dwc->regs, DWC3_DCTL); |
| if (!(reg & DWC3_DCTL_CSFTRST)) |
| - return 0; |
| + goto done; |
| |
| udelay(1); |
| } while (--retries); |
| @@ -170,6 +170,17 @@ static int dwc3_core_soft_reset(struct d |
| phy_exit(dwc->usb2_generic_phy); |
| |
| return -ETIMEDOUT; |
| + |
| +done: |
| + /* |
| + * For DWC_usb31 controller, once DWC3_DCTL_CSFTRST bit is cleared, |
| + * we must wait at least 50ms before accessing the PHY domain |
| + * (synchronization delay). DWC_usb31 programming guide section 1.3.2. |
| + */ |
| + if (dwc3_is_usb31(dwc)) |
| + msleep(50); |
| + |
| + return 0; |
| } |
| |
| /** |
